- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25639 > MQ80C32-25SCD (ATMEL CORP) 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 PDF資料下載
參數(shù)資料
| 型號： | MQ80C32-25SCD |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 39/80頁 |
| 文件大小： | 5152K |
| 代理商： | MQ80C32-25SCD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
239
XMEGA A [MANUAL]
8077I–AVR–11/2012
Figure 21-6. Start bit sampling.
When the clock recovery logic detects a high (idle) to low (start) transition on the RxD line, the start bit detection
sequence is initiated. Sample 1 denotes the first zero-sample, as shown in the figure. The clock recovery logic then uses
samples 8, 9, and 10 for normal mode and samples 4, 5, and 6 for double speed mode to decide if a valid start bit is
received. If two or three samples have a low level, the start bit is accepted. The clock recovery unit is synchronized, and
the data recovery can begin. If two or three samples have a high level, the start bit is rejected as a noise spike, and the
receiver looks for the next high-to-low transition. The process is repeated for each start bit.
21.8.2 Asynchronous Data Recovery
The data recovery unit uses sixteen samples in normal mode and eight samples in double speed mode for each bit.
Figure 21-7 on page 239 shows the sampling process of data and parity bits.
Figure 21-7. Sampling of data and parity bits.
As for start bit detection, an identical majority voting technique is used on the three center samples for deciding of the
logic level of the received bit. The process is repeated for each bit until a complete frame is received. It includes the first
stop bit, but excludes additional ones. If the sampled stop bit is a 0 value, the frame error (FERR) flag will be set.
Figure 21-8 on page 239 shows the sampling of the stop bit in relation to the earliest possible beginning of the next
frame's start bit.
Figure 21-8. Stop bit and next start bit sampling.
A new high-to-low transition indicating the start bit of a new frame can come right after the last of the bits used for
majority voting. For normal speed mode, the first low level sample can be at the point marked (A) in Stop Bit Sampling
and Next Start Bit Sampling. For double speed mode, the first low level must be delayed to point (B). Point (C) marks a
stop bit of full length at nominal baud rate. The early start bit detection influences the operational range of the receiver.
12
34
56
7
8
9
10
11
12
13
14
15
16
12
START
IDLE
0
BIT 0
3
123
4
5
678
12
0
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)
12
34
56
7
8
9
10
11
12
13
14
15
16
1
BIT n
123
4
5
678
1
RxD
Sample
(CLK2X = 0)
Sample
(CLK2X = 1)
12
34
56
7
8
9
10
0/1
STOP 1
123
4
5
60/1
RxD
Sample
(CLK2X = 0)
Sample
(CLK2X = 1)
(A)
(B)
(C)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ80C32E-20SHXXX:D | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52CXXX-16SCD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MF180C51-16R | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| MQ80C32E-20SHXXX:D | 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44 |
| MQ80C32E-36/883D | 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MQ82370-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ8238020 | 制造商:Intel 功能描述:CONTROLLER: OTHER |
| MQ82380-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MQ82380-20/R | 制造商:Rochester Electronics LLC 功能描述: |
| MQ82592 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。