
S1C621A0 TECHNICAL HARDWARE
EPSON
I-65
CHAPTER 3: PERIPHERAL CIRCUITS (Lower Current Dissipation)
3.14 Lower Current Dissipation
The S1C621A0 contains a control register for each circuit
block to realize lower current consumption. The registers are
programmed so as to operate each circuit with a minimum
current. For reference in programming, the following table
summarizes the circuits that can be controlled for lower
current consumption and the in associated registers:
Table 3.14.1
Order of Current Consumption
At initial setting with the CPU in operation mode, the CPU is
ready with OSC3 clock (CLKCHG = 0, in high-speed mode),
the ceramic (CR) oscillation circuit is ON (OSCC = 1), the
REM circuit is ON (REMC = 1), the timer is OFF (TMRUN =
0), the SVD circuit is OFF (SVDON = 0), and the AMP circuit
is OFF (OPON = 0).
It should be noted that various factors affecting current
consumption. For example, a system in which a resistor is
connected to the VADJ pin to control the LCD power (VL1)
differ from a system in which the VADJ pin is shorted to VL1.
Also, characteristics of the LCD panel used will produce a
difference in power consumption to the order of several
micro-amperes.
CPU
CPU operating
frequency
Ceramic (CR)
oscillation
circuit
REM circuit
Timer
SVD circuit
AMP circuit
HALT instruction
CLKCHG
OSCC
REMC
TMRUN
SVDON
OPON
See section 5
"ELECTRICAL CHARACTERISTICS"
Several tens A
Several A (in OSC3 mode)
Several hundreds nA
(OSC3 not used, option used)
Several hundreds nA
Several tens A
Circuit block
Control register
Order of current consumption