
Differences Between the ARM9E-S and the ARM9TDMI
B-2
Copyright 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
B.1
Interface signals
The signal names have prefixes that identify groups of functionally-related signals:
CFG
Shows configuration inputs (typically hard-wired for an embedded
application).
CP
Shows coprocessor expansion interface signals.
DBG
Shows scan-based EmbeddedICE debug support input or output.
Other signals provide the interface for the system designer, which is primarily
memory-mapped.
Table B-1 shows the ARM9E-S signals with their ARM9TDMI hard
macrocell equivalent signals.
Table B-1 ARM9E-S signals and ARM9TDMI hard macrocell equivalents
ARM9E-S signal
Function
ARM9TDMI hard
macrocell equivalent
Note
CFGBIGEND
1 = big-endian configuration.
0 = little-endian configuration.
BIGEND
-
CFGDISLTBIT
1 = disable specific ARMv5T behavior.
0 = enable (default).
--
CFGHIVECS
1 = exception vectors start at 0xFFFF 0000.
0 = exception vectors start at 0x0000 0000.
HIVECS
-
CLK
Rising edge master clock. All inputs are sampled on the
rising edge of CLK.
All timing dependencies are from the rising edge of CLK.
GCLK
a
CLKEN
System memory interface clock enable:
1 = advance the core on rising CLK.
0 = prevent the core advancing on rising CLK.
nWAIT
b
DA[31:0]
32-bit data address output bus, available in the cycle
preceding the memory cycle.
DA[31:0]
c
DABORT
Data Abort.
DABORT
d
DBGCOMMRX
EmbeddedICE communication channel receive buffer full
output.
COMMRX
-
DBGCOMMTX
EmbeddedICE communication channel transmit buffer
empty output.
COMMTX
-
DBGDEWPT
External data watchpoint (tie LOW when not used).
DEWPT
e