40
32000D–04/2011
AVR32
SZ - Size of the page. The following page sizes are provided, see
Table 5-3:
D - Dirty bit. Set if the page has been written to, cleared otherwise. If the memory access is a
store and the D bit is cleared, an Initial Page Write exception is raised.
W - Write through. If set, a write-through cache update policy should be used. Write-back
should be used otherwise. The bit is ignored if the cache only supports write-through or write-
back.
5.2.2.3
Page Table Base Register - PTBR
This register points to the start of the page table structure. The register is not used by hardware,
and can only be modified by software. The register is meant to be used by the MMU-related
exception routines.
5.2.2.4
TLB Exception Address Register - TLBEAR
This register contains the virtual address that caused the most recent MMU-related exception.
The register is updated by hardware when such an exception occurs.
5.2.2.5
MMU Control Register - MMUCR
The MMUCR controls the operation of the MMU. The MMUCR has the following fields:
IRP - Instruction TLB Replacement Pointer. Points to the ITLB entry to overwrite when a new
entry is loaded by the tlbw instruction. The IRP field may be updated automatically in an
IMPLEMENTATION DEFINED manner in order to optimize the replacement algorithm. The
IRP field can also be written by software, allowing the exception routine to implement a
replacement algorithm in software. The IRP field is 6 bits wide, allowing a maximum of 64
Table 5-2.
Access permissions implied by the AP bits
AP
Privileged mode
Unprivileged mode
000
Read
None
001
Read / Execute
None
010
Read / Write
None
011
Read / Write / Execute
None
100
Read
101
Read / Execute
110
Read / Write
111
Read / Write / Execute
Table 5-3.
Page sizes implied by the SZ bits
SZ
Page size
Bits used in VPN
Bits used in PFN
00
1 kB
TLBEHI[31:10]
TLBELO[31:10]
01
4 kB
TLBEHI[31:12]
TLBELO[31:12]
10
64 kB
TLBEHI[31:16]
TLBELO[31:16]
11
1 MB
TLBEHI[31:20]
TLBELO[31:20]