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12
32000D–04/2011
AVR32
Figure 2-7.
The Status Register low halfword
SS - Secure State
This bit is indicates if the processor is executing in the secure state. For more details, see
chap-ter 4. The bit is initialized in an IMPLEMENTATION DEFINED way at reset.
H - Java Handle
This bit is included to support different heap types in the Java Virtual Machine. For more details,
J - Java State
The processor is in Java state when this bit is set. The incoming instruction stream will be
decoded as a stream of Java bytecodes, not RISC opcodes. The bit is cleared at reset. This bit
should not be modified by the user as undefined behaviour may result.
DM - Debug State Mask
If this bit is set, the Debug State is masked and cannot be entered. The bit is cleared at reset,
and can both be read and written by software.
D - Debug State
The processor is in debug state when this bit is set. The bit is cleared at reset and should only be
modified by debug hardware, the breakpoint instruction or the retd instruction. Undefined behav-
iour may result if the user tries to modify this bit manually.
M2, M1, M0 - Execution Mode
These bits show the active execution mode. The settings for the different modes are shown in
supervisor mode after reset. These bits are modified by hardware, or execution of certain
instructions like scall, rets and rete. Undefined behaviour may result if the user tries to modify
these bits manually.
Bit 1 5
Bit 0
Re s e r v e d
C a rry
Ze r o
Sig n
0
-
T
R
B it nam e
In itia l v a lu e
0
L
Q
V
N
Z
C
-
O v er flow
S a tu r a tio n
-
Lo c k
R egis ter R e m ap E n a b le
Sc r a tc h