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參數(shù)資料
| 型號： | MQ80C154-36P883R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 24/46頁 |
| 文件大?。?/td> | 7004K |
| 代理商： | MQ80C154-36P883R |
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156
7593L–AVR–09/12
AT90USB64/128
Figure 16-11. Timer/Counter timing diagram, clear timer on compare match mode, with pres-
caler (f
clk_I/O/8).
16.8
8-bit Timer/Counter register description
16.8.1
TCCR2A – Timer/Counter Control Register A
Bits 7:6 – COM2A1:0: Compare Match Output A mode
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC2A pin
must be set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM22:0 bit setting. Table 16-1 shows the COM2A1:0 bit functionality when the WGM22:0 bits
are set to a normal or CTC mode (non-PWM).
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
7
6
543
2
1
0
COM2A1
COM2A0
COM2B1
COM2B0
––
WGM21
WGM20
TCCR2A
Read/write
R/W
R
R/W
Initial value
0
Table 16-1.
Compare output mode, non-PWM mode.
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected
0
1
Toggle OC2A on Compare Match
1
0
Clear OC2A on Compare Match
1
Set OC2A on Compare Match
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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