![](http://datasheet.mmic.net.cn/100000/IF180C52TXXX-20R_datasheet_3493957/IF180C52TXXX-20R_200.png)
200
32099I–01/2012
AT32UC3L016/32/64
The oscillator is enabled by writing a one to the Enable bit in the 32kHz RC Oscillator Configura-
tion Register (RC32KCR.EN) and disabled by writing a zero to RC32KCR.EN. The oscillator is
also automatically enabled when the sampling mode is requested for the SM33. In this case,
writing a zero to RC32KCR.EN will not disable the RC32K until the sampling mode is no longer
requested.
13.5.13
Generic Clocks
Rev: 1.0.0.0
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF defines a number of generic clocks that
can provide a wide range of accurate clock frequencies.
Each generic clock runs from either clock source listed in the “Generic Clock Sources” table in
the SCIF Module Configuration section. The selected source can optionally be divided by any
even integer up to 512. Each clock can be independently enabled and disabled, and is also
automatically disabled along with peripheral clocks by the Sleep Controller in the Power
Manager.
Figure 13-6. Generic Clock Generation
13.5.13.1
Enabling a generic clock
A generic clock is enabled by writing a one to the Clock Enable bit (CEN) in the Generic Clock
Control Register (GCCTRL). Each generic clock can individually select a clock source by writing
to the Oscillator Select field (OSCSEL). The source clock can optionally be divided by writing a
one to the Divide Enable bit (DIVEN) and the Division Factor field (DIV), resulting in the output
frequency:
where f
SRC is the frequency of the selected source clock, and fGCLK is the output frequency of the
generic clock.
13.5.13.2
Disabling a generic clock
A generic clock is disabled by writing a zero to CEN or entering a sleep mode that disables the
PB clocks. In either case, the generic clock will be switched off on the first falling edge after the
disabling event, to ensure that no glitches occur. After CEN has been written to zero, the bit will
still read as one until the next falling edge occurs, and the clock is actually switched off. When
Divider
O SC SEL
Generic C lock
DIV
0
1
D IVEN
Mask
CEN
Sleep C ontroller
fSRC
fGCLK
G eneric
Clock
Sources
fGCLK
fSRC
2
DIV 1
+
()
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