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參數(shù)資料
| 型號： | MPC99J93ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLK DRIVER IDCS 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時(shí)鐘驅(qū)動器，動態(tài)時(shí)鐘開關(guān) |
| PLL： | 帶旁路 |
| 輸入： | LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 180MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
MPC99J93 REVISION 4 FEBRUARY 6, 2013
5
2013 Integrated Device Technology, Inc.
MPC99J93 Data Sheet
INTELLIGENT DYNAMIC CLOCK SWITCH (IDCS) PLL CLOCK DRIVER
Table 5. AC Characteristics (VCC = 3.3 V 5%, TA = –40C to +85C)(1)
1. AC characteristics apply for parallel output termination of 50
to VCC – 2 V.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Reference Frequency
4 feedback
50
90
MHz
PLL locked
fVCO
VCO Frequency Range(2)
4 feedback
2. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): fref = fVCO FB.
200
360
MHz
fMAX
Output Frequency
QA[1:0]
QB[2:0]
50
100
90
180
MHz
PLL locked
frefDC
Reference Input Duty Cycle
25
75
%
t()
Propagation Delay
SPO, static phase offset(3)
CLK0, CLK1 to any Q
3. CLK0, CLK1 to Ext_FB.
–0.15
0.9
+0.17
1.8
ns
PLL_EN = 1
PLL_EN = 0
VPP
Differential Input Voltage(4)
(peak-to-peak)
4. VPP is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew.
Applicable to CLK0, CLK1 and Ext_FB.
0.25
1.3
V
VCMR
Differential Input Crosspoint Voltage(5)
5. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC)
range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the SPO, device and part-to-part
skew. Applicable to CLK0, CLK1 and Ext_FB.
VCC–1.7
VCC–0.3
V
tsk(O)
Output-to-Output Skew
within QA[2:0] or QB[1:0]
within device
50
80
ps
per/cycle
Rate of Change of Period
QA[1:0](6)
QB[2:0](6)
QA[1:0](7)
QB[2:0](7)
6. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change per
cycle is averaged over the clock switch excursion.
7. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (
180). Delta period change per
cycle is averaged over the clock switch excursion.
20
10
200
100
50
25
400
200
ps
DC
Output Duty Cycle
45
50
55
%
tJIT(CC)
Cycle-to-Cycle Jitter
RMS (1
)
25
ps
tLOCK
Maximum PLL Lock Time
10
ms
tr, tf
Output Rise/Fall Time
0.05
0.70
ns
20% to 80%
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