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參數(shù)資料
| 型號： | MPC99J93ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK DRIVER IDCS 32-LQFP |
| 標準包裝： | 2,000 |
| 類型： | PLL 時鐘驅(qū)動器，動態(tài)時鐘開關(guān) |
| PLL： | 帶旁路 |
| 輸入： | LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 180MHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
DATASHEET
Intelligent Dynamic Clock Switch (IDCS)
PLL Clock Driver
MPC99J93
MPC99J93 REVISION 4 FEBRUARY 6, 2013
1
2013 Integrated Device Technology, Inc.
Product Discontinuance Notice – Last Time Buy Expires on (12/3/2013)
The MPC99J93 is a PLL clock driver designed specifically for redundant clock
tree designs. The device receives two differential LVPECL clock signals from
which it generates five new differential LVPECL clock outputs. Two of the output
pairs regenerate the input signals frequency and phase while the other three
pairs generate 2x, phase aligned clock outputs.
Features
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3-V Operation
32-Lead LQFP Packaging, Pb-Free
Functional Description
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously
monitors both input CLK signals. Upon detection of a failure (CLK stuck HIGH or
LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that
CLK is the primary clock, the IDCS will switch to the good secondary clock and
phase/frequency alignment will occur with minimal output phase disturbance.
The typical phase bump caused by a failed clock is eliminated. (See Applications
Information section).
Figure 1. Block Diagram
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
MPC99J93
INTELLIGENT DYNAMIC
CLOCK SWITCH
PLL CLOCK DRIVER
CLK0
CLK1
Ext_FB
Sel_Clk
DYNAMIC
SWITCH
LOGIC
PLL
PLL_En
2
4
Qb0
Qb1
Qb2
Qa0
Qa1
MR
Man_Override
Clk_Selected
Inp1bad
Inp0bad
Alarm_Reset
200 – 360 MHz
OR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MPC99J93FA | 功能描述:IC CLOCK DRIVER LV 1:5 32-LQFP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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| MPCB-20.0-0-E563 | 制造商:TE Connectivity 功能描述:MPCB-20.0-0-E563 |
| MPCB-20.0-2 | 制造商:TE Connectivity 功能描述:MPCB-20.0-2 |
| MPCBL0001N04Q | 制造商:Intel 功能描述:KENNICOTT (NO FC, 2 X 2.0 GHZ) NO MEMORY OR HARD DRIVE, ROHS - Bulk |
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