參數(shù)資料
型號(hào)： MPC97H73FAR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封裝： LQFP-52
文件頁(yè)數(shù)： 5/20頁(yè)
文件大?。?/td> 206K
代理商： MPC97H73FAR2
MPC97H73
TIMING SOLUTIONS
13
MOTOROLA
the outputs can drive multiple series terminated lines.
Figure 12.
“Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC97H73 clock driver is
effectively doubled due to its capability to drive multiple lines.
Figure 12. Single versus Dual Transmission Lines
14
IN
MPC97H73
OUTPUT
BUFFER
RS = 36
ZO = 50
OutA
14
IN
MPC97H73
OUTPUT
BUFFER
RS = 36
ZO = 50
OutB0
RS = 36
ZO = 50
OutB1
The waveform plots in Figure 13. “Single versus Dual
Line Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both cases
the drive capability of the MPC97H73 output buffer is more
than sufficient to drive 50
transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC97H73. The output waveform in Figure 13.
“Single versus Dual Line Termination Waveforms” shows a
step in the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36
series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50 || 50
RS = 36 || 36
R0 = 14
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
1. Final skew data pending specification.
Figure 13. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
101214
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 14. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
Figure 14. Optimized Dual Line Termination
14
MPC97H73
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 k 22 = 50 k 50
25
= 25
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