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參數(shù)資料
| 型號(hào)： | MPC9774AE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 186K |
| 代理商： | MPC9774AE |
MPC9774
228
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Table 8. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)
1
1.
AC characteristics apply for parallel output termination of 50
to V
TT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fREF
Input Reference Frequency
÷ 8 feedback
÷ 12 feedback
÷ 16 feedback
÷ 24 feedback
÷ 32 feedback
÷ 48 feedback
Input Reference Frequency in PLL Bypass Mode2
2.
In bypass mode, the MPC9774 divides the input reference clock.
25.0
16.6
12.5
8.33
6.25
4.16
62.5
41.6
31.25
20.83
15.625
10.41
250
MHz
PLL locked
PLL bypass
fVCO
VCO Frequency Range3
3.
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): fREF = fVCO ÷ (M VCO_SEL).
200
500
MHz
fMAX
Output Frequency
÷ 4 output
÷ 8 output
÷ 12 output
÷ 16 output
÷ 24 output
50.0
25.0
16.6
12.5
8.33
125.0
62.5
41.6
31.25
20.83
MHz
PLL locked
tPW,MIN
Input Reference Pulse Width4
4.
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF,MIN. E.g. at fREF = 62.5 MHz the
input duty cycle range is 12.5% < DC < 87.5%.
2.0
ns
tR, tF
CCLKx Input Rise/Fall Time
1.0
ns
0.8 to 2.0V
t()
Propagation Delay (static phase offset)5
CCLKx to FB_IN (FB =
÷ 8 and f
REF = 50 MHz)
5.
Static phase offset depends on the reference frequency: t() = +50 ps ± (1÷(120 fREF)) for any reference frequency.
–250
+100
ps
PLL locked
tSK(O)
Output-to-Output Skew6
within QA bank
within QB bank
within QC bank
any output
6.
Refer to Application section for part-to-part skew calculation.
100
125
100
175
ps
DC
Output Duty Cycle
47
50
53
%
tR, tF
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
10
ns
tPZL
Output Enable Time
10
ns
tJIT(CC)
Cycle-to-Cycle Jitter7
7.
Valid for all outputs at the same frequency.
90
ps
tJIT(PER)
Period Jitter6
90
ps
tJIT()
I/O Phase Jitter RMS (1
σ)8
FB =
÷ 8
FB =
÷ 12
FB =
÷ 16
FB =
÷ 24
FB =
÷ 32
FB =
÷ 48
8.
I/O jitter for fVCO = 400 MHz. Refer to APPLICATIONS INFORMATION for I/O jitter at other frequencies and for a jitter calculation for confidence
factors other than 1
σ.
15
49
18
22
26
34
ps
BW
PLL Closed Loop Bandwidth9
FB =
÷ 8
FB =
÷ 12
FB =
÷ 16
FB =
÷ 24
FB =
÷ 32
FB =
÷ 48
9.
–3 dB point of PLL transfer characteristics.
0.50 – 1.80
0.30 – 1.00
0.25 – 0.70
0.17 – 0.40
0.12 – 0.30
0.07 – 0.20
MHz
MHZ
MHz
tLOCK
Maximum PLL Lock Time
10
ms
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