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參數(shù)資料
| 型號(hào)： | MPC9774AE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 186K |
| 代理商： | MPC9774AE |
MPC9774
226
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Table 1. Pin Configuration
Pin
I/O
Type
Function
CCLK0
Input
LVCMOS
PLL reference clock
CCLK1
Input
LVCMOS
Alternative PLL reference clock
FB_IN
Input
LVCMOS
PLL feedback signal input, connect to QFB
CCLK_SEL
Input
LVCMOS
LVCMOS clock reference select
VCO_SEL
Input
LVCMOS
VCO operating frequency select
PLL_EN
Input
LVCMOS
PLL enable/PLL bypass mode select
MR/OE
Input
LVCMOS
Output enable/disable (high-impedance tristate) and device reset
CLK_STOP
Input
LVCMOS
Output enable/clock stop (logic low state)
FSEL_A
Input
LVCMOS
Frequency divider select for bank A outputs
FSEL_B
Input
LVCMOS
Frequency divider select for bank B outputs
FSEL_C
Input
LVCMOS
Frequency divider select for bank C outputs
FSEL_FB[1:0]
Input
LVCMOS
Frequency divider select for the QFB output
QA[4:0]
Output
LVCMOS
Clock outputs (Bank A)
QB[4:0]
Output
LVCMOS
Clock outputs (Bank B)
QC[3:0]
Output
LVCMOS
Clock outputs (Bank C)
QFB
Output
LVCMOS
PLL feedback output. Connect to FB_IN.
GND
Supply
Ground
Negative power supply
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply). It is recommended to use an external RC filter
for the analog power supply pin VCC_PLL. Please see applications section for details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive power
supply for correct operation
Table 2. Function Table (Configuration Controls)
Control
Default
0
1
CCLK_SEL
0
Selects CCLK0 as PLL references signal input
Selects CCKL1 as PLL reference signal input
VCO_SEL
0
Selects VCO
÷ 2. The VCO frequency is scaled by a factor of 2 (high input
frequency range)
Selects VCO
÷ 4. The VCO frequency is
scaled by a factor of 4 (low input frequency
range).
PLL_EN
1
Test mode with the PLL bypassed. The reference clock is substituted for the
internal VCO output. MPC9774 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
Normal operation mode with PLL enabled.
CLK_STOP
1
QA, QB an QC outputs disabled in logic low state. QFB is not affected by
CLK_STOP. CLK_STOP deassertion may cause the initial output clock pulse
to be distorted.
Outputs enabled (active)
MR/OE
1
Outputs disabled (high-impedance state) and reset of the device. During
reset/output disable the PLL feedback loop is open and the internal VCO is
tied to its lowest frequency. The MPC9774 requires reset after any loss of
PLL lock. Loss of PLL lock may occur when the external feedback path is
interrupted. The length of the reset pulse should be greater than one
reference clock cycle (CCLKx). The device is reset by the internal power-on
reset (POR) circuitry during power-up.
Outputs enabled (active)
VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.
Table 3. Function Table (Output Dividers Bank A, B, and C)
VCO_SEL
FSEL_A
QA[4:0]
VCO_SEL
FSEL_B
QB[4:0]
VCO_SEL
FSEL_C
QC[3:0]
00
VCO
÷ 40
0
VCO
÷ 40
0
VCO
÷ 8
01
VCO
÷ 80
1
VCO
÷ 80
1
VCO
÷ 12
10
VCO
÷ 81
0
VCO
÷ 81
0
VCO
÷ 16
11
VCO
÷ 16
1
VCO
÷ 16
1
VCO
÷ 24
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| MPC97H73AE | 功能描述:IC PLL CLK GEN 1:12 3.3V 52-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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