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參數(shù)資料
| 型號： | MPC9772FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 240 MHz, OTHER CLOCK GENERATOR, PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 238K |
| 代理商： | MPC9772FAR2 |
MPC9772
TIMING SOLUTIONS
7
MOTOROLA
tJIT()
I/O Phase Jitter RMS (1
σ)12
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
(VCO=400 MHz)
BW
PLL closed loop bandwidth13
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20 –
3.50
0.70 –
2.50
0.50 –
1.80
0.45 –
1.20
0.30 –
1.00
0.25 –
0.70
0.20 –
0.55
0.17 –
0.40
0.12 –
0.30
0.11 –
0.28
MHz
tLOCK
Maximum PLL Lock Time
10
ms
1.
AC characteristics apply for parallel output termination of 50
to V
TT.
2.
In bypass mode, the MPC9772 divides the input reference clock.
3.
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO ÷ (M VCO_SEL).
4.
The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio:
fXTAL(min, max) = fVCO(min, max) ÷ (M VCO_SEL) and 10 MHz ≤ fXTAL ≤ 25 MHz.
5.
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF, MIN.
6.
The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(), tPW,MIN, DC and fMAX can only be
guaranteed if tR, tF are within the specified range.
7.
Static phase offset depends on the reference frequency. t() [s] = t() [°] ÷ (fREF 360°).
8.
Excluding QSYNC output. See application section for part-to-part skew calculation.
9.
Output duty cycle is DC = (0.5
± 200 ps f
OUT)
100%. E.g. the DC range at fOUT = 100 MHz is 48%<DC<52%. T = output period.
10. Cycle jitter is valid for all outputs in the same divider configuration. See application section for more details.
11. Period jitter is valid for all outputs in the same divider configuration. See application section for more details.
12. I/O jitter is valid for a VCO frequency of 400 MHz. See application section for I/O jitter vs. VCO frequency.
13. –3 dB point of PLL transfer characteristics.
Table 10. AC Characteristics (VCC = 3.3V ± 5%, TA = –40° to +85°C)
1 2 (Continued)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
TA = 0°C
to +70°C
TA = –40°C
to +85°C
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