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參數(shù)資料
| 型號(hào)： | MPC96877VKR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 10/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DRIVER 1:10 SDRAM 52-BGA |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR2，SDRAM |
| 輸入： | 時(shí)鐘 |
| 輸出： | SSTL-18 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 340MHz |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-BGA |
| 包裝： | 帶卷 (TR) |
MPC96877
552
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
1. Total IDD = IDDQ + IADD = FCK* CPD * VDDQ, solving for CPD = (IDDQ + IADD)/(FCK * VDDQ) where FCK is the input Frequency, VDDQ is the power
supply and CPD is the Power Dissipation Capacitance.
Table 5. Electrical Characteristics Over Recommended Free-Air Operating Temperature Range
Description
Parameter
Affected Pins
Test Conditions
AVDD, VDDQ
Min
Max
Unit
All inputs
VIK
II = –18mA
1.7 V
–1.2
V
High output voltage
VOH
IOH = –100 A
1.7 to 1.9 V
VDDQ –0.2
V
IOH = –9 mA
1.7 V
1.1
Low output voltage
VOL
IOL = 100 A
1.7 to 1.9 V
0.1
V
IOL = 9 mA
1.7 V
0.6
Output disable current
IODL
OE = L, VODL = 100 mV
1.7 V
100
A
Output differential voltage
VOD
1.7 V
0.5
V
Input leakage current
II
CK, CK
VI = VDDQ or GND
1.9 V
± 250
A
OE, OS, FBIN, FBIN
VI = VDDQ or GND
1.9 V
± 10
Static supply current IDDQ + IADD
IDDLD
CK and CK = L
1.9 V
500
A
Dynamic Supply current
IDDQ + IADD, see Note 1 for CPD
calculation
IDD
CK and CK = 270 MHz
all outputs open
1.9 V
300
mA
Table 6. Timing Requirements Over Recommended Free-Air Operating Temperature Range
Timing Requirements
AVDD, VDDQ = 1.8 V ± 0.1 V
Unit
Min
Max
Operating clock frequency1, 2
1. The PLL must be able to handle spread spectrum induced skew.
2. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing
parameters. (Used for low speed system debug.)
125
340
MHz
Application clock frequency1, 3
3. Application clock frequency indicates a range over which the PLL must meet all timing parameters.
160
340
MHz
Input clock duty cycle
40
60
%
Stabilization time4
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power
up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal
to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may
be left floating after they have been driven low for one complete clock cycle.
15
s
MPC96877
1.8 V PLL 1:10 Differential SDRAM Clock Driver
NETCOM
IDT 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC96877
6
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