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參數(shù)資料
| 型號(hào)： | MPC96877VKR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52 |
| 封裝： | 4.50 X 7 MM, 0.65 MM PITCH, LEAD FREE, MO-225BA, MAPBGA-52 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 395K |
| 代理商： | MPC96877VKR2 |
Advanced Clock Drivers Devices
12
Freescale Semiconductor
MPC96877
RECOMMENDED FILTERING FOR THE ANALOG POWER SUPPLY (AVDD)
Figure 13. AVDD Filtering
Figure 14. CPD Information
1. Place the 2200 pF capacitor close to the PLL
2. Use a wide trace for the PLL analog power and ground. Connect
PLL and caps to AGND to AGND trace & connect trace to one GND
via (farthest from PLL).
3. Recommended bead: Fair Rite P/N 2506036017Y0 or equivalent
(0.8 Ohm DC max, 600 Ohms @ 100 MHz)
GND
CARD
VIA
Bead
0603
AVDD
1 ohm
R1
AGND
VDDQ
4.7 uF
1206
4.7 uF
1206
4.7 uF
1206
PLL
Dynamic Current (mA) = 8.08169 + 0.25759 Output Frequency (MHz)
D
yn
am
ic
C
u
rre
nt
(m
A
)
0
100
200
300
400
120
110
100
90
80
70
60
50
40
30
20
10
0
Output Frequency (MHz)
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