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參數(shù)資料
| 型號： | MPC96877EP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MO-220VJJD-2, MLF-40 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 221K |
| 代理商： | MPC96877EP |
MPC96877
TIMING SOLUTIONS
7
MOTOROLA
NOTES:
1. There are two different terminations that are used with the following tests. The loadboard in Figure 2 is used to measure the input and output
differential-pair cross voltage only. The loadboard in Figure 3 is used to measure all other tests. For consistency, equal length cables must be
used.
2. Static Phase offset does not include Jitter.
3. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
4. The Output Slew Rate is determined form the IBIS model into the load shown in Figure 4. It is measured single ended.
5. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
Input FBIN, FBIN are recommended to be nearly equal. The 2.5 V/ns slew rates are shown as a recommended target. Compliance with these
Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2
DIMM application.
Table 7. Switching Characteristics over Recommended Free-Air Operating Temperature Range Unless Otherwise Noted
(see Notes)
Description
Parameter
Diagram
AVDD, VDDQ = 1.8 V ± 0.1 V
Unit
Min
Nom
Max
OE to any Y/Y
ten
see Figure 11
8
ns
OE to any Y/Y
tdis
see Figure 11
8
ns
Cycle-to-Cycle period jitter
tjit(cc+)
see Figure 4
0
40
ps
tjit(cc–)
0
–40
ps
Static phase offset
t(
)
see Figure 5
–50
50
ps
Dynamic phase offset
t(
)dyn
see Figure 10
–50
50
ps
Output clock skew
tsk(o)
see Figure 6
40
ps
Period Jitter
tjit(per)
see Figure 7
–40
40
ps
Half -period jitter
tjit(hper)
see Figure 8
–75
75
ps
Output Enable
slr(i)
see Figures 3
and 9
0.5
V/ns
Input clock slew rate, measured single ended
1
2.5
4
Output clock slew rate, measured single ended
slr(o)
see Figures 3
and 9
1.5
2.5
3
V/ns
Output differential-pair cross voltage
VOX
see Figure 2
(VDDQ/2) – 0.1
(VDDQ/2) + 0.1
V
SSC modulation frequency
30
33
kHz
SSC clock input frequency deviation
0.0
–0.5
PLL Loop bandwidth (–3dB from unity gain)
2.0
MHz
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相關代理商/技術參數(shù) |
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|---|---|
| MPC96877VK | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC96877VKR2 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC970 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC972 | 制造商:Motorola Inc 功能描述: |
| MPC972FA | 制造商:Freescale Semiconductor 功能描述: |
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