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參數(shù)資料
| 型號： | MPC9658FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, LQFP-32 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9658FA |
5
MPC9658
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
522
Table 6. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 70°C)a
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency
÷2 feedbackb
PLL mode, external feedback
÷4 feedbackc
Input reference frequency in PLL bypass moded
100
50
0
250
125
250
MHz
PLL locked
fVCO
VCO lock frequency rangee
200
500
MHz
fMAX
Output Frequency
÷2 feedbackc
÷4 feedbackd
100
50
250
125
MHz
PLL locked
VPP
Peak-to-peak input voltage (PCLK)
500
1000
mV
LVPECL
VCMRf
Common Mode Range (PCLK)
1.2
VCC-0.9
V
LVPECL
tPW,MIN
Input Reference Pulse Widthg
2.0
ns
t()
Propagation Delay (static phase offset)
PCLK to FB_IN
fREF=100 MHz
any frequency
–70
–125
+80
+125
ps
PLL locked
tPD
Propagation Delay (PLL and divider bypass)
PCLK to Q0-9
1.0
4.0
ns
tsk(O)
Output-to-output Skewh
120
ps
DC
Output Duty Cyclei
(T
÷2)–400
T
÷2
(T
÷2)+400
ps
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to
2.4V
tPLZ, HZ
Output Disable Time
7.0
ns
tPZL, LZ
Output Enable Time
6.0
ns
tJIT(CC)
Cycle-to-cycle jitter
80
ps
tJIT(PER)
Period Jitter
80
ps
tJIT()
I/O Phase Jitter
fVCO=500 MHz and ÷ 2 feedback, RMS (1σ)j
fVCO=500 MHz and ÷ 4 feedback, RMS (1σ)
5.5
6.5
ps
BW
PLL closed loop bandwidthk
÷ 2 feedbackc
÷ 4 feedbackd
6–20
2–8
MHz
tLOCK
Maximum PLL Lock Time
10
ms
a
AC characteristics apply for parallel output termination of 50
to VTT.
b
÷2 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
c
÷4 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
d
In bypass mode, the MPC9658 divides the input reference clock.
e
The input frequency fref must match the VCO frequency range divided by the feedback divider ratio FB: fref = fVCO ÷ FB.
fVCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t().
g
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN fREF 100% and DCREF,MAX = 100% – DCREF,MIN.
h
See application section for part-to-part skew calculation in PLL zero-delay mode.
i
Output duty cycle is DC = (0.5
± 400 ps fOUT) 100%. E.g. the DC range at fOUT=100MHz is 46%<DC<54%. T = output period.
j
See application section for a jitter calculation for other confidence factors than 1
s and a characteristic for other VCO frequencies.
k
-3 dB point of PLL transfer characteristics.
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