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參數(shù)資料
| 型號： | MPC962309EJ-1H |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER ZD 1:5 3.3V 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 扇出緩沖器（分配），零延遲緩沖 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133.33MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
MPC962305 REVISION 8 JANUARY 8, 2013
4
2013 Integrated Device Technology, Inc.
MPC962305 Data Sheet
LOW-COST, 3.3V ZERO DELAY BUFFEr
Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices(1)
1. All parameters are specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load
10-pF load
10
100
133.33
MHz
Duty Cycle(2) = t2 t1
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Measured at 1.4 V, FOUT = 66.67 MHz
40.0
50.0
60.0
%
t3
Rise Time(2)
Measured between 0.8 V and 2.0 V
2.50
ns
t4
Fall Time(2)
Measured between 0.8 V and 2.0 V
2.50
ns
t5
Output to Output Skew(2)
All outputs equally loaded
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge(2)
Measured at VDD/2
0
350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge(2)
Measured at VDD/2. Measured in PLL Bypass Mode,
MPC962309 device only
15
8.7
ns
t7
Device to Device Skew(2)
Measured at VDD/2 on the CLKOUT pins of devices
0
700
ps
tJ
Cycle to Cycle Jitter(2)
Measured at 66.67 MHz, loaded outputs
200
ps
tLOCK
PLL Lock Time(2)
Stable power supply, valid clock presented on REF pin
1.0
ms
Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices(1)
1. All parameters are specified with loaded outputs.
Parameter
Name
Test Conditions
Min
Typ
Max
Unit
t1
Output Frequency
30-pF load
10-pF load
10
100
133.33
MHz
Duty Cycle(2) = t2
t1
2. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Measured at 1.4 V, FOUT = 66.67 MHz
40.0
50.0
60.0
%
Duty Cycle(2) = t2
t1
Measured at 1.4 V, FOUT < 50 MHz
45.0
55.0
%
t3
Rise Time(2)
Measured between 0.8 V and 2.0 V
1.50
ns
t4
Fall Time(2)
Measured between 0.8 V and 2.0 V
1.50
ns
t5
Output to Output Skew(2)
All outputs equally loaded
250
ps
t6A
Delay, REF Rising Edge to
CLKOUT Rising Edge(2)
Measured at VDD/2
0
350
ps
t6B
Delay, REF Rising Edge to
CLKOUT Rising Edge(2)
Measured at VDD/2. Measured in PLL Bypass Mode,
MPC962309 device only
15
8.7
ns
t7
Device to Device Skew(2)
Measured at VDD/2 on the CLKOUT pins of devices
0
700
ps
t8
Output Slew Rate(2)
Measured between 0.8 V and 2.0 V using Test Circuit #2
1
V/ns
tJ
Cycle to Cycle Jitter(2)
Measured at 66.67 MHz, loaded outputs
200
ps
tLOCK
PLL Lock Time(2)
Stable power supply, valid clock presented on REF pin
1.0
ms
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