參數(shù)資料
型號: MPC962304D-1R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 時鐘及定時
英文描述: 962304 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 0.150 INCH, PLASTIC, SOIC-8
文件頁數(shù): 5/6頁
文件大?。?/td> 84K
代理商: MPC962304D-1R2
MPC962304
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
505
APPLICATIONS INFORMATION
Figure 1. Output-to-Output Skew tSK(O)
Figure 2. Static Phase Offset Test Reference
Figure 3. Output Duty Cycle (DC)
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t6
CCLK
FB_IN
The pin-to-pin skew is defined as the worst case difference in propagation
delay between any similar delay path within a single device
VCC
1.4 V
GND
VCC
1.4 V
GND
t5
The time from the PLL controlled edge to the non-controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
1.4 V
GND
t2
t1
DC = t2/t1 x 100%
Figure 5. Cycle-to-Cycle Jitter
t4
t3
VCC = 3.3 V
2.0
0.8
Figure 6. Output Transition Time Test Reference
The variation in cycle time of a signal between adjacent cycles,
over a random sample of adjacent cycle pairs
tN
tJ = |tN–tN+1|
tN+1
Figure 4. Device-to-Device Skew
VCC
VCC ÷ 2
GND
VCC
VCC ÷ 2
GND
t7
DEVICE 1
DEVICE 2
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