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參數資料
| 型號： | MPC961PACR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數： | 8/10頁 |
| 文件大?。?/td> | 348K |
| 代理商： | MPC961PACR2 |
5
MPC961P
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
492
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.62V. It will then increment towards
the quiescent 3.0V in steps separated by one round trip delay
(in this case 4.0ns).
Figure 5. Single versus Dual Waveforms
TIME (nS)
VOL
TAGE
(V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2
4
6
8
10
12
14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 6 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
Figure 6. Optimized Dual Line Termination
14
MPC961
OUTPUT
BUFFER
RS = 22
ZO = 50
RS = 22
ZO = 50
14
+ 22 k 22 = 50 k 50
25
= 25
SPICE level and IBIS output buffer models are available for
engineers who want to simulate their specific interconnect
schemes.
Using the MPC961P in zero-delay applications
Nested clock trees are typical applications for the
MPC961P. Designs using the MPC961P as LVCMOS PLL fan-
out buffer with zero insertion delay will show significantly lower
clock skew than clock distributions developed from CMOS fan-
out buffers. The external feedback option of the MPC961P
clock driver allows for its use as a zero delay buffer. By using
the QFB output as a feedback to the PLL the propagation delay
through the device is virtually eliminated. The PLL aligns the
feedback clock output edge with the clock input reference
edge resulting a near zero delay through the device. The maxi-
mum insertion delay of the device in zero-delay applications is
measured between the reference clock input and any output.
This effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the output-
to-output skew error relative to the feedback output.
Calculation of part-to-part skew
The MPC961P zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC961P are connected together, the maximum overall tim-
ing uncertainty from the common PCLK input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 7. MPC961P max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
PCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a rms value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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| MPC962305D-1HR2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low-Cost 3.3 V Zero Delay Buffer |
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