參數(shù)資料
型號(hào): MPC9449AE
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 0K
描述: IC CLK BUFF DVDR MUX 3:15 52LQFP
標(biāo)準(zhǔn)包裝: 160
類型: 扇出緩沖器(分配),除法器,多路復(fù)用器
電路數(shù): 1
比率 - 輸入:輸出: 3:15
差分 - 輸入:輸出: 是/無
輸入: LVCMOS,LVPECL
輸出: LVCMOS
頻率 - 最大: 200MHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 52-LQFP
供應(yīng)商設(shè)備封裝: 52-TQFP(10x10)
包裝: 托盤
其它名稱: 800-2220
MPC9449AEIDT-ND
MPC9449 REVISION 6 DECEMBER 21, 2012
4
2012 Integrated Device Technology, Inc.
MPC9449 Data Sheet
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = –40C to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
2.0
VCC 0.3
V
LVCMOS
VIL
Input Low Voltage
0.8
V
LVCMOS
VOH
Output High Voltage
2.4
V
IOH = –24 mA(1)
1. The MPC9449 is capable of driving 50
transmission lines on the incident edge. Each output drives one 50 parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines.
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
250
mV
LVPECL
VCMR(2)
2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
Common Mode Range
PCLK, PCLK
1.0
VCC–0.6
V
LVPECL
VOL
Output Low Voltage
0.55
0.30
V
IOL = 24 mA
IOL = 12 mA
ZOUT
Output Impedance
14 – 17
IIN
Input Current
200
AVIN = VCC or GND
ICCQ
Maximum Quiescent Supply Current
10
mA
All VCC Pins
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40C to 85°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VPP
Peak-to-Peak Input Voltage
PCLK, PCLK
400
1000
mV
LVPECL
VCMR(2)
2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay.
Common Mode Range
PCLK, PCLK
1.0
VCC–0.6
V
LVPECL
fmax
Output Frequency
0
200
MHz
fref
Input Frequency
0
200
MHz
tP, REF
Reference Input Pulse Width
1.5
ns
tr, tf
CCLK0, CCLK1 Input Rise/Fall Time
1.0
ns
0.8 to 2.0 V
tsk(O)
Output-to-Output Skew
Qa outputs
Qb outputs
Qc outputs
Qd outputs
Same Frequency
All outputs
Different Frequencies
All outputs
50
100
200
300
ps
tsk(PP)
Device-to-Device Skew
2.5
ns
tsk(P)
Output Pulse Skew
250
ps
DCREF = 50%
tPLH, HL Propagation Delay
CCLK0 or CCLK1 to any Q
PCLK to any Q
1.0
3.0
5.0
ns
tPLZ, HZ
Output Disable Time
OE to any Q
11
ns
tPZL, LZ
Output Enable Time
OE to any Q
11
ns
tr, tf
Output Rise/Fall Time(3)
3. An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
0.1
1.0
ns
0.55 to 2.4 V
tJIT(CC)
Cycle-to-Cycle Jitter
RMS (1
)TBD
ps
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