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參數(shù)資料
| 型號(hào)： | MPC940 |
| 廠商： | Motorola, Inc. |
| 元件分類： | FPGA |
| 英文描述： | 80000 SYSTEM GATE 1.5 VOLT FPGA |
| 中文描述： | 低壓1:18時(shí)鐘分配芯片 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 91K |
| 代理商： | MPC940 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 0.2
Motorola, Inc. 1997
6/97
"
!
The MPC940 is a 1:18 low voltage clock distribution chip. The device
features the capability to select either a differential LVPECL or an LVTTL/
LVCMOS compatible input. The 18 outputs are LVCMOS or LVTTL
compatible and feature the drive strength to drive 50
series or parallel
terminated transmission lines. With output–to–output skews of 150ps, the
MPC940 is ideal as a clock distribution chip for the most demanding of
synchronous systems. For a similar product with a larger number of
outputs, please consult the MPC941 data sheet.
LVPECL or LVCMOS/LVTTL Clock Input
150ps Maximum Targeted Output–to–Output Skew
Drives Up to 36 Independent Clock Lines
Maximum Output Frequency of 250MHz
32–Lead TQFP Packaging
3.3V VCC Supply Voltage
With a low output impedance (
≈
20
), in both the HIGH and LOW logic
states, the output buffers of the MPC940 are ideal for driving series
terminated transmission lines. More specifically, each of the 18 MPC940
outputs can drive two series terminated 50
transmission lines. With this
capability, the MPC940 has an effective fanout of 1:36 in applications
where each line drives a single load. With this level of fanout, the
MPC940 provides enough copies of low skew clocks for most high
performance synchronous systems.
The differential LVPECL inputs of the MPC940 allow the device to interface directly with a LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.
The MPC940 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
LOW VOLTAGE
1:18 CLOCK
DISTRIBUTION CHIP
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC941 | LOW VOLTAGE 1:27 CLOCK DISTRIBUTION CHIP |
| MPC942C | LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
| MPC9443 | 80000 SYSTEM GATE 1.5 VOLT FPGA |
| MPC9447 | 80000 SYSTEM GATE 1.5 VOLT FPGA |
| MPC9447D | 3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC940L | 制造商:Motorola Inc 功能描述: |
| MPC940LAC | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 FSL 1-18 LVCMOS/LVPE CL to LVCMOS Fanout RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC940LACR2 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 FSL 1-18 LVCMOS/LVPE CL to LVCMOS Fanout RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC940LFA | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 2.5 3.3V 250MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC940LFAR2 | 功能描述:時(shí)鐘驅(qū)動(dòng)器及分配 FSL 1-18 LVCMOS/LVPE CL to LVCMOS Fanout RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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