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參數(shù)資料
| 型號(hào)： | MPC93R51FAR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 155K |
| 代理商： | MPC93R51FAR2 |
MPC93R51
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
135
mum overall timing uncertainty from the common TCLK input
to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 3. MPC93R51 max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
TCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
Table 8: Confidence Facter CF
CF
Probability of clock edge within the distribution
± 1s
0.68268948
± 2s
0.95449988
± 3s
0.99730007
± 4s
0.99993663
± 5s
0.99999943
± 6s
0.99999999
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (
± 3s) is assumed, resulting in a worst
case timing uncertainty from input to any output of -251 ps to
351 ps relative to TCLK (VCC=3.3V and fVCO = 400 MHz):
tSK(PP) =
[–50ps...150ps] + [–150ps...150ps] +
[(17ps
@ –3)...(17ps @ 3)] + tPD, LINE(FB)
tSK(PP) =
[–251ps...351ps] + tPD, LINE(FB)
Above equation uses the maximum I/O jitter number shown
in the AC characteristic table for VCC=3.3V (17 ps RMS). I/O
jitter is frequency dependant with a maximum at the lowest
VCO frequency (200 MHz for the MPC93R51). Applications
using a higher VCO frequency exhibit less I/O jitter than the AC
characteristic limit. The I/O jitter characteristics in Figure 4 can
be used to derive a smaller I/O jitter number at the specific
VCO frequency, resulting in tighter timing limits in zero-delay
mode and for part-to-part skew tSK(PP).
Figure 4. Max. I/O Jitter (RMS) versus frequency for
VCC=3.3V
Power Supply Filtering
The MPC93R51 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Noise on the VCCA
(PLL) power supply impacts the device characteristics, for
instance I/O jitter. The MPC93R51 provides separate power
supplies for the output buffers (VCC) and the phase-locked
loop (VCCA) of the device.The purpose of this design technique
is to isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase-locked loop. In a digi-
tal system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the VCCA pin for the MPC93R51.
Figure 5 illustrates a typical power supply filter scheme. The
MPC93R51 frequency and phase stability is most susceptible
to noise with spectral content in the 100kHz to 20MHz range.
Therefore the filter should be designed to target this range.
The key parameter that needs to be met in the final filter design
is the DC voltage drop across the series filter resistor RF. From
the data sheet the ICCA current (the current sourced through
the VCCA pin) is typically 3 mA (5 mA maximum), assuming
that a minimum of 3.0V must be maintained on the VCCA pin.
The resistor RF shown in Figure 5 “VCCA Power Supply Filter”
must have a resistance of 5–15
W to meet the voltage drop
criteria.
2
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