- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45375 > MPC92439FN (FREESCALE SEMICONDUCTOR INC) 900 MHz, OTHER CLOCK GENERATOR, PQCC28 PDF資料下載
參數(shù)資料
| 型號(hào)： | MPC92439FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 288K |
| 代理商： | MPC92439FN |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)當(dāng)前第15頁(yè)第16頁(yè)
Advanced Clock Drivers Devices
8
Freescale Semiconductor
MPC92439
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH to LOW transition on the
S_LOAD input will latch the new divide values into the
counters. Figure 6 illustrates the timing diagram for both a
parallel and a serial load of the MPC92439 synthesizer.
M[6:0] and N[1:0] are normally specified once at power-up
through the parallel interface, and then possibly again
through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine-tune the clock as the ability to control the serial interface
becomes available.
Using the Test and Diagnosis Output TEST
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. Although it is possible to select the node
that represents FOUT, the LVCMOS output is not able to
toggle fast enough for higher output frequencies and should
only be used for test and diagnosis.
The T2, T1 and T0 control bits are preset to ‘000' when
P_LOAD is LOW so that the PECL FOUT outputs are as jitter-
free as possible. Any active signal on the TEST output pin will
have detrimental affects on the jitter of the PECL output pair.
In normal operations, jitter specifications are only guaranteed
if the TEST output is static. The serial configuration port can
be used to select one of the alternate functions for this pin.
Most of the signals available on the TEST output pin are
useful only for performance verification of the MPC92439
itself. However, the PLL bypass mode may be of interest at
the board level for functional debug. When T[2:0] is set to 110
the MPC92439 is placed in PLL bypass mode. In this mode
the S_CLOCK input is fed directly into the M and N dividers.
The N divider drives the FOUT differential pair and the M
counter drives the TEST output pin. In this mode the
S_CLOCK input could be used for low speed board level
functional test or debug. Bypassing the PLL and driving
FOUT directly gives the user more control on the test clocks
sent through the clocktree shows the functional setup of the
PLL bypass mode. Because the S_CLOCK is a CMOS level
the input frequency is limited to 200 MHz. This means the
fastest the FOUT pin can be toggled via the S_CLOCK is 100
MHz as the divide ratio of the Post-PLL divider is 2 (if N = 1).
Note that the M counter output on the TEST output will not be
a 50% duty cycle.
Figure 6. Serial Interface Timing Diagram
Power Supply Filtering
The MPC92439 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCC_PLL pin impacts the device
characteristics. The MPC92439 provides separate power
supplies for the digital circuitry (VCC) and the internal PLL
(VCC_PLL) of the device. The purpose of this design technique
is to try and isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a controlled environment such as an evaluation
board, this level of isolation is sufficient. However, in a digital
system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may
be required. The simplest form of isolation is a power supply
filter on the VCC_PLL pin for the MPC92439. Figure 7
Table 10. Test and Debug Configuration for TEST
T[2:0]
TEST Output
T2
T1
T0
000
12-bit shift register out(1)
1. Clocked out at the rate of S_CLOCK\
0
1
Logic 1
010
fXTAL ÷ 2
0
1
M-Counter out
100
FOUT
1
0
1
Logic 0
1
0
M-Counter out in PLL-bypass mode
111
FOUT
÷ 4
Table 11. Debug Configuration for PLL Bypass(1)
1. T[2:0] = 110. AC specifications do not apply in PLL bypass
mode
Output
Configuration
FOUT
S_CLOCK
÷ N
TEST
M-Counter out(2)
2. Clocked out at the rate of S_CLOCK
÷ (2N)
S_CLOCK
S_DATA
S_LOAD
M[6:0]
N[1:0]
P_LOAD
T2 T1
T0
N1
N0
M6
M5
M4
M3
M2
M1
M0
M, N
First
Bit
Last
Bit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC92439FAR2 | 900 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| MPC92439ACR2 | 900 MHz, OTHER CLOCK GENERATOR, PQFP32 |
| MPC92439EIR2 | 900 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| MPC92474AC | 700 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| MPC930FAR2 | 140 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92439KLF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
| MPC92469 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:400 MHz Low Voltage PECL Clock Synthesizer w/Spread Spectrum |
| MPC92469AC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 LVPECL Clock Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92469ACR2 | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| MPC9259 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:900 MHz LOW VOLTAGE LVDS CLOCK SYNTHESIZER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。