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參數(shù)資料
| 型號(hào)： | MPC92439FN |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 288K |
| 代理商： | MPC92439FN |
Advanced Clock Drivers Devices
Freescale Semiconductor
7
MPC92439
PROGRAMMING INTERFACE
Programming the MPC92439
Programming the MPC92439 amounts to properly
configuring the internal PLL dividers to produce the desired
synthesized frequency at the output. The output frequency
can be represented by this formula:
fOUT = fXTAL M ÷ N(1)
where fXTAL is the crystal frequency, M is the PLL feedback-
divider and N is the PLL post-divider. The input frequency and
the selection of the feedback divider M is limited by the VCO-
frequency range. fXTAL and M must be configured to match
the VCO frequency range of 400 to 900 MHz in order to
achieve stable PLL operation:
MMIN = fVCO,MIN ÷ (fXTAL) and
(2)
MMAX = fVCO,MAX ÷ (fXTAL)(3)
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between M = 25
and M = 56. Table 8 shows the usable VCO frequency and M
divider range for other example input frequencies. Assuming
that a 16 MHz input frequency is used, equation (1) reduces
to:
fOUT = 16 M ÷ N(4)
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Example Calculation for an 16 MHz Input Frequency
For example, if an output frequency of 384 MHz was
desired, the following steps would be taken to identify the
appropriate M and N values. 384 MHz falls within the
frequency range set by an N value of 2, so N[1:0]=00. For N
= 2, FOUT = 8M and M = FOUT
÷8. Therefore, M = 384 ÷ 8 =
48, so M[6:0] = 0110000. Following this procedure a user can
generate any whole frequency between 50 MHz and 900
MHz. The size of the programmable frequency steps will be
equal to:
fSTEP = fXTAL ÷ N(5)
APPLICATIONS INFORMATION
Jitter Performance of the MPC92439
of the MPC92439 across its specified VCO frequency range.
The cycle-to-cycle and period jitter is a function of the VCO
frequency and the output divider N. The general trend is that
as the output frequency increases (higher VCO frequency
and lower N-divider) the MPC92439 output jitter decreases.
Optimum jitter performance can be achieved at higher VCO
and output frequencies. The maximum cycle-to-cycle and
period jitter published in Table 7 correspond to the jitter
performance at the lowest VCO frequency limit).
Figure 4. MPC92439 Cycle-to-cycle Jitter
Figure 5. MPC92439 Period Jitter
Using the Parallel and Serial Interface
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW to HIGH transition
will latch the information present on the M[6:0] and N[1:0]
inputs into the M and N counters. When the P_LOAD signal
is LOW the input latches will be transparent and any changes
on the M[6:0] and N[1:0] inputs will affect the FOUT output
pair. To use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 12 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two, and
the M register with the final eight bits of the data stream on
the S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M6). A pulse on the S_LOAD pin after
Table 9. Output Frequency Range for fXTAL = 16 MHz
N
FOUT
FOUT Range
FOUT Step
10
Value
00
2
8
M
200-450 MHz
8 MHz
01
4
M
100-225 MHz
4 MHz
10
8
2
M
50-112.5 MHz
2 MHz
11
1
16
M
400-900 MHz
16 MHz
Cycle-to-cycle jitter vs. VCO frequency
Parameter: Output divider N
0
10
20
30
40
50
60
70
400
500
600
700
800
900
VCO frequency [MHz]
tjit(cyc)
[ps]
rms
N=÷1
N=÷2
N=÷4
N=÷8
Period jitter vs. VCO frequency
Parameter: Output divider N
0
5
10
15
20
25
30
35
40
400
500
600
700
800
900
VCO frequency [MHz]
tjit(cyc)
[ps]
rms
N=÷1
N=÷2
N=÷4
N=÷8
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