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參數(shù)資料
| 型號： | MPC92432AER2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 1360 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LEAD FREE, LQFP-48 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大小： | 412K |
| 代理商： | MPC92432AER2 |
Advanced Clock Drivers Devices
10
Freescale Semiconductor
MPC92432
LOAD and GET are inverse command to each other.
LOAD updates the PLL dividers and GET updates the
configuration registers. A fast and convenient way to change
the PLL frequency is to use the INC (increment M) and DEC
(decrement M) commands of the synthesizer. INC (DEC)
directly increments (decrements) the PLL-feedback divider M
and immediately changes the PLL frequency by the smallest
step G (see Table 7 for the frequency granularity G). The INC
and DEC commands are designed for multiple and rapid PLL
frequency changes as required in frequency margining
applications. INC and DEC do not require the user to update
the PLL dividers by the LOAD command, INC and DEC do
not update the PLL_L and PLL_H registers either (use LOAD
for an initial PLL divider setting and, if desired, use GET to
read the PLL configuration). Note that the synthesizer does
not check any boundary conditions such as the VCO
frequency range. Applying the INC and DEC commands
could result in invalid VCO frequencies (VCO frequency
beyond lock range).
Register Maps
Register 0x00 (PLL_L) contains the least significant bits of
the PLL feedback divider M.
Register content:
M[7:0]
PLL feedback-divider M, bits 7–0
Register 0x01 (PLL_H) contains the two most significant
bits of the PLL feedback divider M, four bits to control the PLL
post-dividers N and the PLL pre-divider P. The bit 0 in PLL_H
register indicates the lock condition of the PLL and is set by
the synthesizer automatically. The LOCK state is a copy of
the PLL lock signal output (LOCK). A write-access to LOCK
has no effect.
Register content:
M[9:8]
PLL feedback-divider M, bits 9–8
NA[2:0]
NB
P
PLL pre-divider P, see Table 8
LOCK
Copy of LOCK output signal (read-only)
Note that the LOAD command is required to update the
PLL dividers by the content of both PLL_L and PLL_H
registers.
Register 0xF0 (CMD) is a write-only command register.
The purpose of CMD is to provide a fast way to increase or
decrease the PLL frequency and to update the registers. The
register accepts four commands, INC (increment M), DEC
(decrement M), LOAD and GET (update registers). It is
recommended to write the INC, DEC commands only after a
valid PLL configuration is achieved. INC and DEC only affect
the M-divider of the PLL (PLL feedback). Applying INC and
DEC commands can result in a PLL configuration beyond the
specified lock range and the PLL may loose lock. The
MPC92432 does not verify the validity of any commands
such as LOAD, INC, and DEC. The INC and DEC commands
change the PLL feedback divider without updating PLL_L
and PLL_H.
I2C — Register Access in Parallel Mode
The MPC92432 supports the configuration of the
synthesizer through the parallel interlace (PLOAD = 0) and
serial interface (PLOAD = 1). Register contents and the
divider configurations are not changed when the user
switches from parallel mode to serial mode. However, when
switching from serial mode to parallel mode, the PLL dividers
immediately reflect the logical state of the hardware pins
M[9:0], NA[2:0], NB, and P.
Applications using the parallel interface to obtain a PLL
configuration can use the serial interface to verify the divider
settings. In parallel mode (PLOAD = 0), the MPC92432
allows read-access to PLL_L and PLL_H through I2C (if
PLOAD = 0, the current PLL configuration is stored in PLL_L,
PLL_H. The GET command is not necessary and also not
supported in parallel mode). After changing from parallel to
serial mode (PLOAD = 1), the last PLL configuration is still
stored in PLL_L, PLL_H. The user now has full write and read
access to both configuration registers through the I2C bus
and can change the configuration at any time.
Table 13. Configuration Registers
Address
Name
Content
Access
0x00
PLL_L
Least significant 8 bits of M
R/W
0x01
PLL_H Most significant 2 bits of M, P, NA,
NB, and lock state
R/W
0xF0
CMD
Command register (write only)
W only
Table 14. PLL_L (0x00, R/W) Register
Bit
765
432
10
Name
M7
M6
M5
M4
M3
M2
M1
M0
Table 15. PLL_H (0x01, R/W) Register
Bit
765
432
1
0
Name
M9
M8
NA2
NA1
NA0
NB
P
LOCK
Table 16. CMD (0xF0): PLL Command (Write-Only)
Command
Op-Code
Description
INC
xxxx0001b
(0x01)
Increase internal PLL frequency
M:=M+1
DEC
xxxx0010b
(0x02)
Decrease internal PLL frequency
M:=M-1
LOAD
xxxx0100b
(0x04)
Update the PLL divider config.
PLL divider M, N, P:=PLL_L, PLL_H
GET
xxxx1000b
(0x08)
Update the configuration registers
PLL_L, PLL_H:=PLL divider M, N, P
Table 17. PLL Configuration in Parallel and Serial Modes
PLL
Configuration
Parallel
Serial (Registers
PLL_L, PLL_H)
M[9:0]
Set pins M9–M0
M[9:0] (R/W)
NA[2:0]
Set pins NA2...NA0
NA[2:0] (R/W)
NB
Set pin NB
NB (R/W)
P
Set pin P
P (R/W)
LOCK status
LOCK pin 26
LOCK (Read only)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92432FA | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:1360 MHz Dual Output LVPECL Clock Synthesizer |
| MPC92433 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:1428 MHz Dual Output LVPECL Clock Synthesizer |
| MPC92433AE | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92433AER2 | 功能描述:時鐘合成器/抖動清除器 FSL 1428MHz Dual Out put LVPECL Clock Syn RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92439 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:900MHz, Low Voltage, LVPECL Clock Syntheesizer |
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