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參數(shù)資料
| 型號： | MPC9239FNR2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 900 MHz, OTHER CLOCK GENERATOR, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 136K |
| 代理商： | MPC9239FNR2 |
4
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9239/D
Rev 2, 03/2003
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
417
900 MHz Low Voltage LVPECL
Clock Synthesizer
The MPC9239 is a 3.3V compatible, PLL based clock synthesizer tar-
geted for high performance clock generation in mid-range to high-perfor-
mance telecom, networking and computing applications. With output fre-
quencies from 3.125 MHz to 900 MHz and the support of differential
LVPECL output signals the device meets the needs of the most demand-
ing clock applications.
Features
3.125 MHz to 900 MHz synthesized clock output signal
Differential LVPECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference input
3.3V power supply
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
28 PLCC and 32 LQFP packaging
SiGe Technology
Ambient temperature range 0°C to + 70°C
Pin and function compatible to the MC12439
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator or external reference clock signal is multiplied by the PLL. The VCO within the PLL operates over a
range of 800 to 1800 MHz. Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal
oscillator frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase lock.
The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1800 MHz). The M-value must
be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50
to VCC – 2.0V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[6:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW–to–HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[6:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating. The serial interface centers on a twelve bit shift register. The shift register shifts once per rising edge of the
S_CLOCK input. The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this
document. The configuration latches will capture the value of the shift register on the HIGH–to–LOW edge of the S_LOAD input.
See the programming section for more information. The TEST output reflects various internal node values, and is controlled by
the T[2:0] bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST
output. The PWR_DOWN pin, when asserted, will synchronously divide the FOUT by 16. The power down sequence is clocked
by the PLL reference clock, thereby causing the frequency reduction to happen relatively slowly. Upon de–assertion of the
PWR_DOWN pin, the FOUT input will step back up to its programmed frequency in four discrete increments.
MPC9239
900 MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
FN SUFFIX
28–LEAD PLCC PACKAGE
CASE 776
FA SUFFIX
32 LEAD LQFP PACKAGE
CASE 873A
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC92429 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:400 MHz Low Voltage PECL Clock Synthesizer |
| MPC92429AC | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92429ACR2 | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92429EI | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MPC92429EIR2 | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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