參數(shù)資料
型號： MPC9239FAR2
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 900 MHz, OTHER CLOCK GENERATOR, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, MS-026BBA, LQFP-32
文件頁數(shù)： 10/14頁
文件大小： 353K
代理商： MPC9239FAR2
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MPC9239
Table 6. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (fREF_EXT, PWR_DOWN, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.8
V
LVCMOS
IIN
Input Current(1)
1. Inputs have pull-down resistors affecting the input current.
±200
A
VIN = VCC or GND
Differential Clock Output fOUT(2)
2. Outputs terminated 50
to VTT = VCC – 2 V.
VOH
Output High Voltage(3)
3. The MPC9239 TEST output levels are compatible to the MC12429 output levels. The MPC9239 is capable of driving 25
loads.
VCC–1.02
VCC–0.74
V
LVPECL
VOL
Output Low Voltage(3)
VCC–1.95
VCC–1.60
V
LVPECL
Test and Diagnosis Output TEST
VOH
Output High Voltage(3)
2.0
V
IOH = –0.8 mA
VOL
Output Low Voltage(3)
0.55
V
IOL = 0.8 mA
Supply Current
ICC_PLL
Maximum PLL Supply Current
20
mA
VCC_PLL Pins
ICC
Maximum Supply Current
62
100
mA
All VCC Pins
Table 7. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
1. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fXTAL
Crystal Interface Frequency Range
10
20
MHz
fVCO
VCO Frequency Range(2)
2. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL 2 M.
800
1800
MHz
fMAX
Output Frequency
N = 11 (
÷ 1)
N = 00 (
÷ 2)
N = 01 (
÷ 4)
N = 10 (
÷ 8)
400
300
100
50
900
450
225
112.5
MHz
PWR_DOWN = 0
fS_CLOCK
Serial Interface Programming Clock Frequency(3)
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. Refer to the application section for more details.
0
10
MHz
tP,MIN
Minimum Pulse Width
(S_LOAD, P_LOAD)
50
ns
DC
Output Duty Cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.05
0.3
ns
20% to 80%
tS
Setup Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
ns
tS
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
ns
tJIT(CC)
Cycle-to-Cycle Jitter
N = 11 (
÷ 1)
N = 00 (
÷ 2)
N = 01 (
÷ 4)
N = 10 (
÷ 8)
60
90
120
160
ps
tJIT(PER)
Period Jitter
N = 11 (
÷ 1)
N = 00 (
÷ 2)
N = 01 (
÷ 4)
N = 10 (
÷ 8)
40
65
90
120
ps
tLOCK
Maximum PLL Lock Time
10
ms
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相關(guān)代理商/技術(shù)參數(shù)
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