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參數(shù)資料
| 型號(hào)： | MPC9100 |
| 廠商： | Motorola, Inc. |
| 英文描述： | DUAL PLL CLOCK GENERATOR |
| 中文描述： | 雙PLL時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 111K |
| 代理商： | MPC9100 |
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1996
10/96
The MPC9100 is a dual PLL phase locked loop clock generator. The
device synthesizes a 14.318 MHz input reference to provide a buffered
copy of the input reference, a 31.3344MHz clock output and a 45.1584
clock output.
The device features a fully integrated crystal oscillator as the clock
reference source. No external components are required other than the
14.318 MHz crystal. The TCLK input is used only for factory test and
cannot be used as the PLL clock reference. To reduce total die area the
PLL loop filter capacitors are brought outside the chip. The FCAP pins are
used to connect these capacitors to the internal PLL’s. 0.01
μ
f capacitors
are recommended.
The device features three synchronous output enable pins to allow for
shutting down specific clocks. When driven to a logic LOW the OE pins
will freeze the selected clock in its low state. Internal timing has been
established that guarantee transition into and out of the freeze state will
not produce output glitches. These control inputs have internal pull up
resistors so that they will default to the output active state.
The TEST0–2 pins allow for the testing of the internal logic of the
device. Most of the states are reserved for factory test use with one
exception. When the TEST 0 pin is driven low the internal state machines
will be reset and the outputs will be driven into high impedance. The
TEST pins also have internal pull up resistors such that they will default
into the normal operation mode of the chip.
The MPC9100 features separate internal power buses to try to isolate
the output noise from the internal PLL’s and the other outputs. The VCCA
pins are the power supply pins for the analog PLL’s, the VCCI pin is the
power supply for the internal core logic and the VCCO’s are the power
pins for the output buffers. All of these pins should be tied to a common
power plane on the printed circuit board.
FUNCTION TABLES
TEST2
TEST1
TEST0
Function
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Factory Test
Factory Test
Factory Test
Factory Test
Factory Test
Factory Test
Master Reset/Tristate
Normal Operation
OE_XX
Function
0
1
Output LOW
Output Active
PIN DESCRIPTION
Pin
Description
Q_31
Q_14
Q_45
VCCO_XX
GNDO_XX
VCCI
GNDI
VCCAX
GNDAX
XTAL1
XTAL2
TCLK
FCAPXX
FCAPXXP
31.3344MHz Output
14.318MHz Output
45.1584MHz Output
Output Buffer Power Supply
Output Buffer Ground
Core Logic Power Supply
Core Logic Ground
PLL Power Supply
PLL Ground
Crystal Oscillator Input
Crystal Oscillator Input
LVCMOS Reference Clock Input
PLL Filter Capacitor Input
PLL Filter Capacitor Input
DUAL PLL
CLOCK GENERATOR
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
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