參數(shù)資料
型號: MPC9108
廠商: Motorola, Inc.
元件分類: FPGA
英文描述: 80000 SYSTEM GATE 1.5 VOLT FPGA
中文描述: 多重輸出時鐘合成器
文件頁數(shù): 1/4頁
文件大?。?/td> 67K
代理商: MPC9108
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1997
1/97
The MPC9108 is a multiple CMOS output clock synthesizer targeted
for disk drive applications. The device interfaces to a 20MHz crystal as its
frequency source. From this source the device provides a buffered copy
of the 20MHz clock as well as synthesized 40MHz and 50MHz output
clocks.
Fully Integrated PLL
Fully Integrated Crystal Oscillator
Low cost, low jitter design
Low cost 8–lead SOIC packaging
In addition to the output clock frequencies, the MPC9108 also offers a
lock indicator output. When the internal PLL achieves phase and
frequency lock the CLK_LOCK signal will go HIGH. The pin will remain
HIGH unless the PLL loses lock due to input clock or power supply
disturbances.
The XTALIN pin (pin 1) can be over–driven with a standard 5V CMOS
signal. When an externally generated reference is used the XTALOUT pin
should be left open.
The MPC9108 operates from a 5.0V supply across the commercial
temperature range of 0
°
C to 70
°
C. The 8–lead SOIC package is used to
optimize board space efficiency as well as minimizing cost.
Pinout: 8–Lead SOIC
(Top View)
8
1
XTALOUT
XTALIN
7
2
CLK_LOCK
VDD
6
3
CLK2
GND
5
4
CLK3
CLK1
Pin Descriptions
Pin Name
Pin Number
I/O
Function
XTALIN
1
I
20MHz Crystal Connection, External Reference Point
VDD
2
+5V Power Supply
GND
3
Ground
CLK1
4
O
20MHz Output, Buffer Xtal Output
CLK2
5
O
50MHz Output, PLL Controlled
CLK3
6
O
40MHz Output, PLL Controlled
CLK_LOCK
7
O
HIGH When PLL is Locked
XTALOUT
8
O
Crystal Oscillator Connection
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
MULTIPLE OUTPUT
CLOCK SYNTHESIZER
D SUFFIX
PLASTIC SOIC
CASE 751–03
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