
20-20
MPC866 PowerQUICC Family User’s Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
TSA Implementation
the effects of changing the delay from frame sync to data valid.
Figure 20-14. One Clock Delay from Sync to Data (xFSD = 01)
Figure 20-15. No Delay from Sync to Data (xFSD = 00)
constant frame sync delay of one bit.
13, 29
GMx
Grant mode for TDMa/b
0 GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is supported
internally. The grant is signalled by one bit of the Rx frame and is marked by setting
1 IDL mode. A grant mechanism is supported if the corresponding SICR[GRn] are set. The grant
is a sample of the L1GRx signal while L1TSYNCx is asserted. This grant mechanism implies
the IDL Interface.”Note that if GMa = 1, then the RTS4 signal on ports B and C functions as
L1RQa. (The RTS4 function is still available on port D.)
Note that if GMb = 1, then the RTS3 signal on ports B and C functions as L1RQb. (The RTS3
function is still available on port D.)
14–15,
30–31
TFSDx
Transmit frame sync delay for TDMa/b. Determines the delay between the Tx sync and the rst bit
of the Tx frame. If CRTx is set, the Rx sync is used as the common sync, and the TFSDx bits refer
to this common sync.
00 No bit delay. The rst bit of the frame is sent on the same clock as the sync.
01 1-bit delay
10 2-bit delay
11 3-bit delay
Table 20-5. SIMODE Field Descriptions (continued)
Bits
Name
Description
L1CLK
Data
(CE=0)
L1SYNC
(FE=1)
Bit-0
Bit-1
Bit-2
Bit-3
Bit-4
Bit-0
One Clock Delay from Sync Latch to First Bit of Frame
Bit-5
End of Frame
L1CLK
Data
(CE=0)
L1SYNC
(FE=1)
Bit-0
Bit-1
Bit-2
Bit-3
Bit-4
No Delay from Sync Latch to First Bit of Frame
Bit-2
Bit-1
Bit-0