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H-18
MPC866 PowerQUICC Family User’s Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 44 Fast Ethernet Controller (FEC)
H.18 Chapter 44 Fast Ethernet Controller (FEC)
Table H-19. FEC Signal Descriptions
Name
Pin
Number
Description
IRQ7
MII_TX_CLK
N12
Interrupt request 7—This input is one of the eight external lines that can request (by
means of the internal Interrupt Controller) a service routine from the core.
MII transmit clock—Input clock that provides the timing reference for TX_EN, TXD, and
TX_ER.
Note: MII_TXCLK becomes active as soon as ECNTRL[ETHER_EN] is set.
IRQ7 must be masked in the SIU, see Section 10.5.4.2, “SIU Interrupt Mask Register
(SIMASK).
PD[15]
MII_RXD[3]
M14
General-purpose I/O port D bit 15—This is bit 15 of the general-purpose I/O port D.
MII receive data 3—Input signal RXD[3] represents bit 3 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted.
PD[14]
MII_RXD[2]
N16
General-purpose I/O port D bit 14—This is bit 14 of the general-purpose I/O port D.
MII receive data 2—Input signal RXD[2] represents bit 2 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted.
PD[13]
MII_RXD[1]
K13
General-purpose I/O port D bit 13—This is bit 13 of the general-purpose I/O port D.
MII receive data 1—Input signal RXD[1] represents bit 1 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted.
PD[12]
MII_MDC
N15
General-purpose I/O port D bit 12—This is bit 12 of the general-purpose I/O port D.
MII management data clock—Output clock provides a timing reference to the PHY for
data transfers on the MDIO signal.
PD[11]
RXD3
MII_TX_ER
P16
General-purpose I/O port D bit 11—This is bit 11 of the general-purpose I/O port D.
RXD3—Receive data for serial channel 3.
MII transmit error—Output signal when asserted for one or more clock cycles while
TX_EN is asserted shall cause the PHY to transmit one or more illegal symbols.
Asserting TX_ER has no effect when operating at 10 Mbps or when TX_EN is negated.
PD[10]
TXD3
MII_RXD[0]
R15
General-purpose I/O port D bit 10—This is bit 10 of the general-purpose I/O port D.
TXD3—Transmit data for serial channel 3.
MII receive data 0—Input signal RXD[0] represents bit 0 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted. In 10 Mbps serial mode,
RXD[0] is used and RXD[1–3] are ignored.
PD[9]
RXD4
MII_TXD[0]
N14
General-purpose I/O port D bit 9—This is bit 9 of the general-purpose I/O port D.
RXD4—Receive data for serial channel 4.
MII transmit data 0—Output signal TXD[0] represents bit 0 of the nibble of data when
TX_EN is asserted and has no meaning when TX_EN is negated. In 10Mbps serial
mode, TXD[0] is used and TXD[1–3] are ignored.
PD[8]
TXD4
MII_RX_CLK
M13
General-purpose I/O port D bit 8—This is bit 8 of the general-purpose I/O port D.
TXD4—Transmit data for serial channel 4.
MII receive clock—Input clock which provides a timing reference for RX_DV, RXD, and
RX_ER.
PD[7]
RTS3
MII_RX_ER
T15
General-purpose I/O port D bit 7—This is bit 7 of the general-purpose I/O port D.
RTS3—Active-low request to send output indicates that SCC3 is ready to transmit data.
MII receive error—When Input signal RX_ER and RX_DV are asserted, the PHY has
detected an error in the current frame. When RX_DV is not asserted, RX_ER has no
effect.