
15-6
MPC866 PowerQUICC Family User’s Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chip-Select Programming Common to the GPCM and UPM
Figure 15-4. Basic Memory Controller Operation
15.3 Chip-Select Programming Common to the GPCM
and UPM
The GPCM and the UPMs use the memory controller registers as specied in
Table 15-1.Table 15-1. Memory Controller Register Usage
Register
Used by the GPCM
Used by a UPM
Base register bank 0–7 register (BRx)
√√
Option register bank 0–7 register (ORx)
√√
Memory status register (MSTAT)
√√
Memory command register (MCR)
√
Machine A mode register (MAMR)
√
Machine B mode register (MBMR)
√
Memory data register (MDR)
√
Memory address register (MAR)
√
Memory periodic timer prescaler register (MPTPR)
√
Address
Comparator
Bank Select
UPMB
GPCM
MS
Field
Signals
Timing
Generator
Signals
Timing
Generator
MUX
Internal/External Memory Access Request Select
Address (A),
Address
Type (AT)
External Signals
UPMA