
MOTOROLA
Chapter 29. Serial Management Controllers (SMCs)
29-7
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Common SMC Settings and Congurations
Table 29-2. SMC UART and Transparent Parameter RAM Memory Map
Offset 1
Name
Width
Description
0x00
RBASE Hword RxBDs and TxBDs base address. (BD table pointer) Dene starting points in the dual-port
RAM of the set of BDs for the SMC send and receive functions. They allow exible
partitioning of the BDs. By selecting RBASE and TBASE entries for all SMCs and by setting
W in the last BD in each list, BDs are allocated for the send and receive side of every SMC.
Initialize these entries before enabling the corresponding channel. Conguring BD tables
of two enabled SMCs to overlap causes erratic operation. RBASE and TBASE should be a
multiple of eight.
0x02
TBASE Hword
0x04
RFCR
Byte
0x05
TFCR
Byte
0x06
MRBLR Hword Maximum receive buffer length. The most bytes the MPC866 writes to a Rx buffer before
moving to the next buffer. It can write fewer bytes than MRBLR if a condition like an error
or end-of-frame occurs, but it cannot exceed MRBLR. Rx buffers should not be smaller than
MRBLR. SMC Tx buffers are unaffected by MRBLR.
Tx buffers can be individually given varying lengths through the data length eld. MRBLR
can be changed while an SMC is operating only if it is done in a single bus cycle with one
16-bit move (not two 8-bit bus cycles back-to-back). This occurs when the CP shifts control
to the next RxBD, so the change does not take effect immediately. To guarantee the exact
RxBD on which the change occurs, change MRBLR only while the SMC receiver is
disabled. MRBLR should be greater than zero and should be even if character length
exceeds 8 bits.
0x08
RSTATE
Word Rx internal state. Can be used only by the CP.
0x0C
—
Word Rx internal data pointer. 2 Updated by the SDMA channels to show the next address in the
buffer to be accessed.
0x10
RBPTR Hword RxBD pointer. Points to the next BD for each SMC channel that the receiver transfers data
to when it is in idle state, or to the current BD during frame processing. After a reset or when
the end of the BD table is reached, the CP initializes RBPTR to the value in RBASE. Most
applications never need to write RBPTR, but it can be written when the receiver is disabled
or when no receive buffer is in use.
0x12
—
Hword Rx internal byte count.
2 A down-count value initialized with the MRBLR value and
decremented with every byte the SDMA channels write.
0x14
—
Word Rx temp.
2 Can be used only by the CP.
0x18
TSTATE
Word Tx internal state. Can be used only by the CP.
0x1C
—
Word Tx internal data pointer.
2 Updated by the SDMA channels to show the next address in the
buffer to be accessed.
0x20
TBPTR Hword TxBD pointer. Points to the next BD for each SMC channel the transmitter transfers data
from when it is in idle state or to the current BD during frame transmission. After reset or
when the end of the table is reached, the CP initializes TBPTR to the TBASE value. Most
applications never need to write TBPTR, but it can be written when the transmitter is
disabled or when no transmit buffer is in use. For instance, after a STOP TRANSMIT or
GRACEFUL STOP TRANSMIT
command is issued and the frame completes its transmission.
0x22
—
Hword Tx internal byte count.
2 A down-count value initialized with the TxBD data length and
decremented with every byte the SDMA channels read.
0x24
—
Word Tx temp.
2 Can be used only by the CP.