參數(shù)資料
型號: MPC8572LVTATLE
廠商: Freescale Semiconductor
文件頁數(shù): 20/138頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023FCPBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.2GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
116
Freescale Semiconductor
Package Description
25. When operating in DDR2 mode, connect Dn_MDIC[0] to ground through 18.2-
Ω (full-strength mode) or 36.4-Ω (half-strength
mode) precision 1% resistor, and connect Dn_MDIC[1] to GVDD through 18.2-
Ω (full-strength mode) or 36.4-Ω
(half-strength mode) precision 1% resistor. When operating in DDR3 mode, connect Dn_MDIC[0] to ground through 20-
Ω
(full-strength mode) or 40-
Ω (half-strength mode) precision 1% resistor, and connect Dn_MDIC[1] to GVDD through 20-Ω
(full-strength mode) or 40-
Ω (half-strength mode) precision 1% resistor. These pins are used for automatic calibration of the
DDR IOs.
26. These pins should be connected to XVDD_SRDS1.
27. These pins should be pulled to ground (XGND_SRDS1) through a 300-
Ω (±10%) resistor.
28. These pins should be left floating.
29. These pins should be pulled up to TVDD through a 2–10 K
Ω resistor.
30. These pins have other manufacturing or debug test functions. It is recommended to add both pull-up resistor pads to OVDD
and pull-down resistor pads to GND on board to support future debug testing when needed.
31. DDRCLK input is only required when the MPC8572E DDR controller is running in asynchronous mode. When the DDR
controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not
required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode. See the
MPC8572E
PowerQUICC III Integrated Host Processor Family Reference Manual Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”,
section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding
DDR controller operation in asynchronous and synchronous modes.
32. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and
RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.
33. These pins should be pulled to ground (GND).
34. These pins are sampled at POR for General Purpose configuration use by software. Their value has no impact on the
functionality of the hardware.
Table 76. MPC8572E Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
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