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參數(shù)資料
| 型號： | MPC8572LVTATLE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 19/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | MPU POWERQUICC III 1023FCPBGA |
| 標準包裝： | 1 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 1.2GHz |
| 電壓： | 1.1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BBGA，F(xiàn)CBGA |
| 供應商設備封裝： | 1023-FCPBGA（33x33） |
| 包裝： | 托盤 |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
Freescale Semiconductor
115
Package Description
N/C
No Connection
A16, A20, B16, B17,
B19, B20, C17, C18,
C19, D28, R31, T17,
V23, W23, Y22, Y23,
Y24, AA24, AB24,
AC24, AC26, AC27,
AC29, AD31, AE29,
AJ25, AK28, AL31,
AM21
——
17
Note:
1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
local bus controller section, and is not mentioned in the DMA section even though the pin also functions as DMA_REQ2.
2. Recommend a weak pull-up resistor (2–10 K
Ω) be placed on this pin to OVDD.
4. This pin is an open drain signal.
5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the processor is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kO pull-down resistor. However, if the
signal is intended to be high after reset, and if there is any device on the net which might pull down the value of the net at
reset, then a pullup or active driver is needed.
6. Treat these pins as no connects (NC) unless using debug address functionality.
7. The value of LA[29:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-k
Ω pull-up or pull-down
resistors. See Section 19.2, “CCB/SYSCLK PLL Ratio.”
8. The value of LALE, LGPL2 and LBCTL at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-k
Ω
pull-up or pull-down resistors. See the Section 19.3, “e500 Core PLL Ratio.”
9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin therefore be described as an I/O for boundary scan.
10. If this pin is configured for local bus controller usage, recommend a weak pull-up resistor (2-10 K
Ω) be placed on this pin to
BVDD, to ensure no random chip select assertion due to possible noise and so on.
11. This output is actively driven during reset rather than being three-stated during reset.
12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13. These pins are connected to the VDD/GND planes internally and may be used by the core power supply to improve tracking
and regulation.
14. Internal thermally sensitive diode.
15. If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a safe state
during reset.
16. This pin is only an output in FIFO mode when used as Rx Flow Control.
17. Do not connect.
18. These are test signals for factory use only and must be pulled up (100
Ω - 1 KΩ) to OVDD for normal machine operation.
19. Independent supplies derived from board VDD.
20. Recommend a pull-up resistor (~1 K
Ω) be placed on this pin to OVDD.
21. The following pins must NOT be pulled down during power-on reset: DMA1_DACK[0:1], EC5_MDC, HRESET_REQ,
TRIG_OUT/READY_P0/QUIESCE, MSRCID[2:4], MDVAL, ASLEEP.
22. This pin requires an external 4.7-k
Ω pull-down resistor to prevent PHY from seeing a valid Transmit Enable before it is
actively driven.
23. This pin is only an output in eTSEC3 FIFO mode when used as Rx flow control.
24. TSEC2_TXD[1] is used as cfg_dram_type. IT MUST BE VALID AT POWER-UP, EVEN BEFORE HRESET ASSERTION.
Table 76. MPC8572E Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
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