參數(shù)資料
型號(hào): MPC8572EVTAVND
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 30/138頁
文件大?。?/td> 1502K
代理商: MPC8572EVTAVND
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
125
System Design Information
21 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8572E.
21.1
System Clocking
This device includes seven PLLs, as follows:
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 19.2, “CCB/SYSCLK PLL Ratio.”
2. There are two core PLLs whose ratios are individually configurable. Each e500 core PLL
generates the core clock as a slave to the platform clock. The frequency ratio between the e500
core clock and the platform clock is selected using the e500 PLL ratio configuration bits as
3. The DDR Complex PLL generates the clocking for the DDR Controllers
4. The local bus PLL generates the clock for the local bus.
5. There is a PLL for the SerDes1 block to be used for PCI Express and Serial Rapid IO Interfaces.
6. There is a PLL for the SerDes2 block to be used for SGMII Interface.
21.2
Power Supply Design
21.2.1
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins
(AVDD_PLAT, AVDD_CORE0, AVDD_CORE1, AVDD_DDR, AVDD_LBIU, AVDD_SRDS1 and
AVDD_SRDS2 respectively). The AVDD level should always be equivalent to VDD, and preferably these
voltages will be derived directly from VDD through a low frequency filter scheme such as the following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in Figure 62, one to each of the
AVDD pins. By providing independent filters to each PLL the opportunity to cause noise injection from
one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of the 1023 FC-PBGA footprint, without the inductance of vias.
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MPC8572EVTAVNE 功能描述:微處理器 - MPU 38H R211 Enc NoPb 1500 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572LPXARLD 功能描述:微處理器 - MPU CSM SNPB 1067 LOW PWR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572LPXARLE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1067LP - Bulk
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MPC8572LPXATLE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1200LP - Bulk