參數資料
型號： MPC8572EVTAVND
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
封裝： 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數： 21/138頁
文件大?。?/td> 1502K
代理商： MPC8572EVTAVND
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
117
Package Description
25. When operating in DDR2 mode, connect Dn_MDIC[0] to ground through an 18.2-
Ω (full-strength mode) or 36.4-Ω
(half-strength mode) precision 1% resistor, and connect Dn_MDIC[1] to GVDD through an 18.2-
Ω (full-strength mode) or
36.4-
Ω (half-strength mode) precision 1% resistor. When operating in DDR3 mode, connect Dn_MDIC[0] to ground through
an 20-
Ω (full-strength mode) or 40-Ω (half-strength mode) precision 1% resistor, and connect Dn_MDIC[1] to GVDD through
an 20-
Ω (full-strength mode) or 40-Ω (half-strength mode) precision 1% resistor. These pins are used for automatic
calibration of the DDR IOs.
26. These pins should be connected to XVDD_SRDS1.
27. These pins should be pulled to ground (XGND_SRDS1) through a 300-
Ω (±10%) resistor.
28. These pins should be left floating.
29. These pins should be pulled up to TVDD through a 2–10 K
Ω resistor.
30. These pins have other manufacturing or debug test functions. It’s recommended to add both pull-up resistor pads to OVDD
and pull-down resistor pads to GND on board to support future debug testing when needed.
31. DDRCLK input is only required when the MPC8572E DDR controller is running in asynchronous mode. When the DDR
controller is configured to run in synchronous mode via POR setting cfg_ddr_pll[0:2]=111, the DDRCLK input is not
required. It is recommended to tie it off to GND when DDR controller is running in synchronous mode. See the
MPC8572E
PowerQUICC III Integrated Host Processor Family Reference Manual Rev.0, Table 4-3 in section 4.2.2 “Clock Signals”,
section 4.4.3.2 “DDR PLL Ratio” and Table 4-10 “DDR Complex Clock PLL Ratio” for more detailed description regarding
DDR controller operation in asynchronous and synchronous modes.
32. EC_GTX_CLK125 is a 125-MHz input clock shared among all eTSEC ports in the following modes: GMII, TBI, RGMII and
RTBI. If none of the eTSEC ports is operating in these modes, the EC_GTX_CLK125 input can be tied off to GND.
33. These pins should be pulled to ground (GND).
34. These pins are sampled at POR for General Purpose configuration use by software. Their value has no impact on the
functionality of the hardware.
Table 73. MPC8572E Pinout Listing (continued)
Signal
Signal Name
Package Pin Number
Pin Type
Power
Supply
Notes
相關PDF資料
PDF描述
MPC8572PXAULB 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
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MPC8572VTAVLD 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023
MPC8572CVTAULD 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA1023
相關代理商/技術參數
參數描述
MPC8572EVTAVNE 功能描述:微處理器 - MPU 38H R211 Enc NoPb 1500 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572LPXARLD 功能描述:微處理器 - MPU CSM SNPB 1067 LOW PWR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572LPXARLE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1067LP - Bulk
MPC8572LPXATLD 功能描述:微處理器 - MPU CSM SNPB 1200 LOW PWR RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8572LPXATLE 制造商:Freescale Semiconductor 功能描述:38H R211 NOE SNPB 1200LP - Bulk
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