參數(shù)資料
型號: MPC8572CVTARND
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 1067 MHz, MICROPROCESSOR, PBGA1023
封裝: 33 X 33 MM, LEAD FREE, PLASTIC, FCBGA-1023
文件頁數(shù): 130/138頁
文件大?。?/td> 1502K
代理商: MPC8572CVTARND
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
91
Serial RapidIO
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
17.1
DC Requirements for Serial RapidIO SD1_REF_CLK and
SD1_REF_CLK
For more information, see Section 15.2, “SerDes Reference Clocks.”
17.2
AC Requirements for Serial RapidIO SD1_REF_CLK and
SD1_REF_CLK
Table 61 lists the AC requirements.
17.3
Equalization
With the use of high speed serial links, the interconnect media will cause degradation of the signal at the
receiver. Effects such as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss
can be large enough to degrade the eye opening at the receiver beyond what is allowed in the specification.
To negate a portion of these effects, equalization can be used. The most common equalization techniques
that can be used are as follows:
A passive high pass filter network placed at the receiver. This is often referred to as passive
equalization.
The use of active circuits in the receiver. This is often referred to as adaptive equalization.
17.4
Explanatory Note on Transmitter and Receiver Specifications
AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at
three baud rates (a total of six cases) are described.
The parameters for the AC electrical specifications are guided by the XAUI electrical interface specified
in Clause 47 of IEEE 802.3ae-2002.
XAUI has similar application goals to serial RapidIO, as described in Section 8.1. The goal of this standard
is that electrical designs for serial RapidIO can reuse electrical designs for XAUI, suitably modified for
applications at the baud intervals and reaches described herein.
Table 61. SD
n_REF_CLK and SDn_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Comments
tREF
REFCLK cycle time
10(8)
ns
8 ns applies only to serial RapidIO
with 125-MHz reference clock
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in
the period of any two adjacent REFCLK
cycles
——
80
ps
tREFPJ
Phase jitter. Deviation in edge location with
respect to mean edge location
–40
40
ps
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