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參數(shù)資料
| 型號： | MPC8572CPXAVLD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1500 MHz, MICROPROCESSOR, PBGA1023 |
| 封裝： | 33 X 33 MM, PLASTIC, FCBGA-1023 |
| 文件頁數(shù)： | 23/138頁 |
| 文件大?。?/td> | 1502K |
| 代理商： | MPC8572CPXAVLD |
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MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
119
Clocking
The DDR memory controller can run in either synchronous or asynchronous mode. When running in
synchronous mode, the memory bus is clocked relative to the platform clock frequency. When running in
asynchronous mode, the memory bus is clocked with its own dedicated PLL with clock provided on
DDRCLK input pin. Table 75 provides the clocking specifications for the memory bus.
As a general guideline when selecting the DDR data rate or platform (CCB) frequency, the following
procedures can be used:
Start with the processor core frequency selection;
Once the processor core frequency is determined, select the platform (CCB) frequency from the
Check the CCB to SYSCLK ratio to verify a valid ratio can be choose from Table 76;
If the desired DDR data rate can be same as the CCB frequency, use the synchronous DDR mode;
Otherwise, if a higher DDR data rate is desired, use asynchronous mode by selecting a valid DDR
data rate to DDRCLK ratio from Table 79. Please note that in asynchronous mode, the DDR data
rate must be greater than the platform (CCB) frequency. In other words, running DDR data rate
lower than the platform (CCB) frequency in asynchronous mode is not supported by MPC8572E.
Verify all clock ratios to ensure that there is no violation to any clock and/or ratio specification.
19.2
CCB/SYSCLK PLL Ratio
The CCB clock is the clock that drives the e500 core complex bus (CCB), and is also called the platform
clock. The frequency of the CCB is set using the following reset signals, as shown in Table 76:
SYSCLK input signal
Binary value on LA[29:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that, in synchronous mode, the DDR data rate is the determining factor in selecting the CCB bus frequency,
since the CCB frequency must equal the DDR data rate. In asynchronous mode, the memory bus clock
frequency is decoupled from the CCB bus frequency.
Table 75. Memory Bus Clocking Specifications
Characteristic
Min
Max
Unit
Notes
Memory bus clock frequency
200
400
MHz
1, 2, 3, 4
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to Section 19.2, “CCB/SYSCLK PLL Ratio,” Section 19.3, “e500 Core PLL Ratio,” and
Section 19.4, “DDR/DDRCLK PLL Ratio,” for ratio settings.
2. The Memory bus clock refers to the MPC8572E memory controllers’ Dn_MCK[0:5] and Dn_MCK[0:5] output clocks, running
at half of the DDR data rate.
3. In synchronous mode, the memory bus clock speed is half the platform clock frequency. In other words, the DDR data rate is
the same as the platform (CCB) frequency. If the desired DDR data rate is higher than the platform (CCB) frequency,
asynchronous mode must be used.
4. In asynchronous mode, the memory bus clock speed is dictated by its own PLL. Refer to Section 19.4, “DDR/DDRCLK PLL
Ratio.” The memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the
DDR data rate.
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