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| 型號： | MPC8560VTAQLB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783 |
| 封裝： | 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783 |
| 文件頁數(shù)： | 70/108頁 |
| 文件大小： | 1379K |
| 代理商： | MPC8560VTAQLB |
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MPC8560 Integrated Processor Hardware Specifications, Rev. 4
64
Freescale Semiconductor
RapidIO
The eye pattern for a data signal is generated by making a large number of recordings of the signal and
then overlaying the recordings. The number of recordings used to generate the eye shall be large enough
that further increasing the number of recordings used does not cause the resulting eye pattern to change
from one that complies with the RapidIO transmit mask to one that does not. Each data signal in the
interface shall be carrying random or pseudo-random data when the recordings are made. If
pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long
enough that increasing the length of the sequence does not cause the resulting eye pattern to change from
one that complies with the RapidIO transmit mask to one that does not comply with the mask. The data
carried by any given data signal in the interface may not be correlated with the data carried by any other
data signal in the interface. The zero-crossings of the clock associated with a data signal shall be used as
the timing reference for aligning the multiple recordings of the data signal when the recordings are
overlaid.
While the method used to make the recordings and overlay them to form the eye pattern is not specified,
the method used shall be demonstrably equivalent to the following method. The signal under test is
repeatedly recorded with a digital oscilloscope in infinite persistence mode. Each recording is triggered by
a zero-crossing of the clock associated with the data signal under test. Roughly half of the recordings are
triggered by positive-going clock zero-crossings and roughly half are triggered by negative-going clock
zero-crossings. Each recording is at least 1.9 UI in length (to ensure that at least one complete eye is
formed) and begins 0.5 UI before the trigger point (0.5 UI before the associated clock zero-crossing).
Depending on the length of the individual recordings used to generate the eye pattern, one or more
complete eyes will be formed. Regardless of the number of eyes, the eye whose center is immediately to
the right of the trigger point is the eye used for compliance testing.
An example of an eye pattern generated using the above method with recordings 3 UI in length is shown
in Figure 44. In this example, there is no skew between the signal under test and the associated clock used
to trigger the recordings. If skew was present, the eye pattern would be shifted to the left or right relative
to the oscilloscope trigger point.
.
Figure 44. Example Driver Output Eye Pattern
0
+
–
V
OD
0.5 UI
1.0 UI
Oscilloscope
(Recording)
Trigger Point
Eye Pattern
Eye Used for
Compliance
Testing
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