參數(shù)資料
型號(hào)： MPC8560VTAQLB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù)： 47/108頁(yè)
文件大?。?/td> 1379K
代理商： MPC8560VTAQLB
MPC8560 Integrated Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
43
CPM
9.2 CPM AC Timing Specifications
Table 34 and Table 35 provide the CPM input and output AC timing specifications, respectively.
Output low voltage
(IOL = 8.0 mA)
VOL
—0.5
V
1
Output high voltage
(IOH = –2.0 mA)
VOH
2.4
—
V
1
Output low voltage
(IOL = 3.2 mA)
VOL
—0.4
V
1
Note:
1. This specification applies to the following pins: PA[0–31], PB[4–31], PC[0–31], and PD[4–31].
2. VIL(max) for the IIC interface is 0.8 V rather than the 1.5 V specified in the IIC standard
Table 34. CPM Input AC Timing Specifications 1
Characteristic
Symbol 2
Min 3
Unit
FCC inputs—internal clock (NMSI) input setup time
tFIIVKH
6ns
FCC inputs—internal clock (NMSI) hold time
tFIIXKH
0ns
FCC inputs—external clock (NMSI) input setup time
tFEIVKH
2.5
ns
FCC inputs—external clock (NMSI) hold time
tFEIXKHb2
ns
SCC/SPI inputs—internal clock (NMSI) input setup time
tNIIVKH
6ns
SCC/SPI inputs—internal clock (NMSI) input hold time
tNIIXKH
0ns
SCC/SPI inputs—external clock (NMSI) input setup time
tNEIVKH
4ns
SCC/SPI inputs—external clock (NMSI) input hold time
tNEIXKH
2ns
TDM inputs/SI—input setup time
tTDIVKH
4ns
TDM inputs/SI—hold time
tTDIXKH
3ns
COL/CRS width high (FCC)
tFCCH
1.5
CLK
Notes:
1.Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of Serial Clock.
Timings are measured at the pin.
2.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example,
tFIIVKH symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the
valid state (V) relative to the reference clock tFCC (K) going to the high (H) state or setup time. And tTDIXKH
symbolizes the TDM timing (TD) with respect to the time the input signals (I) reach the invalid state (X) relative to
the reference clock tFCC (K) going to the high (H) state or hold time.
3.PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER
inputs are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as
asynchronous.
Table 33. CPM DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Max
Unit
Notes
相關(guān)PDF資料
PDF描述
MPC8560CVTAQLC 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
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