參數(shù)資料
型號： MPC8560PXAPFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù)： 60/108頁
文件大小： 2170K
代理商： MPC8560PXAPFB
MPC8560 Integrated Processor Hardware Specifications, Rev. 3.1
Freescale Semiconductor
55
I2C
Figure 36 provides the AC test load for the I2C.
Figure 36. I2C AC Test Load
Figure 37 shows the AC timing diagram for the I2C bus.
Figure 37. I2C Bus AC Timing Diagram
Bus free time between a STOP and START condition
tI2KHDX
1.3
—
s
Noise margin at the LOW level for each connected device
(including hysteresis)
VNL
0.1
× OVDD
—
V
Noise margin at the HIGH level for each connected device
(including hysteresis)
VNH
0.2
× OVDD
—
V
Notes:
1.The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C
clock reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that
the data with respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low
(L) state or hold time. Also, tI2PVKH symbolizes I
2C timing (I2) for the time that the data with respect to the stop
condition (P) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.MPC8560 provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3.The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4.CB = capacitance of one bus line in pF.
6.Guaranteed by design.
Table 40. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 39).
Parameter
Symbol 1
Min
Max
Unit
Output
OVDD/2
RL = 50
Z0 = 50
Sr
S
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
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