參數(shù)資料
型號(hào): MPC8560PX833LD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁(yè)數(shù): 13/104頁(yè)
文件大小: 1244K
代理商: MPC8560PX833LD
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
16
Freescale Semiconductor
Clock Timing
4.2
TSEC Gigabit Reference Clock Timing
Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
MPC8560.
4.3
RapidIO Transmit Clock Input Timing
Table 9 provides the RapidIO transmit clock input (RIO_TX_CLK_IN) AC timing specifications for the
MPC8560.
4.4
Real Time Clock Timing
Table 10 provides the real time clock (RTC) AC timing specifications for the MPC8560.
Table 8. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
fG125
—125
MHz
EC_GTX_CLK125 cycle time
tG125
—8
ns
EC_GTX_CLK125 rise and fall time
LVDD=2.5
LVDD=3.3
tG125R, tG125F
——
0.75
1
ns
2
EC_GTX_CLK125 duty cycle
GMII, TBI
RGMII, RTBI
tG125H/tG125
45
47
55
53
%1, 3
Notes:
1. Timing is guaranteed by design and characterization.
2. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for LVDD=2.5V, and from 0.6 and 2.7V for
LVDD=3.3V.
3. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
Table 9. RIO_TX_CLK_IN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
RIO_TX_CLK_IN frequency
fRCLK
125
MHz
RIO_TX_CLK_IN cycle time
tRCLK
——
8
ns
RIO_TX_CLK_IN duty cycle
tRCLKH/tRCLK
48
52
%
1
Notes:
1. Requires
±100 ppm long term frequency stability. Timing is guaranteed by design and characterization.
Table 10. RTC AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
RTC clock high time
tRTCH
2 x
tCCB_CLK
——
ns
RTC clock low time
tRTCL
2 x
tCCB_CLK
——
ns
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