參數(shù)資料
型號(hào)： MPC8560PX833JB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 833 MHz, RISC PROCESSOR, PBGA783
封裝： 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 62/104頁(yè)
文件大小： 1244K
代理商： MPC8560PX833JB
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
60
Freescale Semiconductor
RapidIO
The peak differential signal of the transmitter output or receiver input, is A – B volts.
The peak-to-peak differential signal of the transmitter output or receiver input, is 2
× (A – B) volts.
Figure 42. Differential Peak-to-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using numerical values, consider the case where a LVDS transmitter has a
common mode voltage of 1.2 V and each signal has a swing that goes between 1.4 and 1.0 V. Using these
values, the peak-to-peak voltage swing of the signals TD, TD, RD, and RD is 400 mV. The differential
signal ranges between 400 and –400 mV. The peak differential signal is 400 mV, and the peak-to-peak
differential signal is 800 mV.
A timing edge is the zero-crossing of a differential signal. Each skew timing parameter on a parallel bus
is synchronously measured on two signals relative to each other in the same cycle, such as data to data,
data to clock, or clock to clock. A skew timing parameter may be relative to the edge of a signal or to the
middle of two sequential edges.
Static skew represents the timing difference between signals that does not vary over time regardless of
system activity or data pattern. Path length differences are a primary source of static skew.
Dynamic skew represents the amount of timing difference between signals that is dependent on the activity
of other signals and varies over time. Crosstalk between signals is a source of dynamic skew.
Eye diagrams and compliance masks are a useful way to visualize and specify driver and receiver
performance. This technique is used in several serial bus specifications. An example compliance mask is
shown in Figure 43. The key difference in the application of this technique for a parallel bus is that the data
is source synchronous to its bus clock while serial data is referenced to its embedded clock. Eye diagrams
reveal the quality (cleanness, openness, goodness) of a driver output or receiver input. An advantage of
using an eye diagram and a compliance mask is that it allows specifying the quality of a signal without
requiring separate specifications for effects such as rise time, duty cycle distortion, data dependent
dynamic skew, random dynamic skew, etc. This allows the individual semiconductor manufacturer
maximum flexibility to trade off various performance criteria while keeping the system performance
constant.
In using the eye pattern and compliance mask approach, the quality of the signal is specified by the
compliance mask. The mask specifies the maximum permissible magnitude of the signal and the minimum
permissible eye opening. The eye diagram for the signal under test is generated according to the
specification. Compliance is determined by whether the compliance mask can be positioned over the eye
diagram such that the eye pattern falls entirely within the unshaded portion of the mask.
Serial specifications have clock encoded with the data, but the LP-LVDS physical layer defined by
RapidIO is a source synchronous parallel port so additional specifications to include effects that are not
found in serial links are required. Specifications for the effect of bit to bit timing differences caused by
static skew have been added and the eye diagrams specified are measured relative to the associated clock
in order to include clock to data effects. With the transmit output (or receiver input) eye diagram, the user
can determine if the transmitter output (or receiver input) is compliant with an oscilloscope with the
appropriate software.
A V
B V
TD or RD
相關(guān)PDF資料
PDF描述
MPC8560PXAQFB 32-BIT, 1000 MHz, RISC PROCESSOR, PBGA783
MPC8560CPX667JD 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
MPC8560CPX667LC 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
MPC8560CVT833LC 32-BIT, 883 MHz, RISC PROCESSOR, PBGA783
MPC8560VT667LC 32-BIT, 667 MHz, RISC PROCESSOR, PBGA783
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MPC8560PX833LB 功能描述:微處理器 - MPU PQ 3 8560-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560PX833LC 功能描述:微處理器 - MPU PQ 3 8560-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560PXAQFB 功能描述:微處理器 - MPU PQ 3 DRACO-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560PXAQFC 功能描述:微處理器 - MPU PQ 3 DRACO-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
MPC8560VT667LB 功能描述:微處理器 - MPU PQ 3 8560-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*