參數(shù)資料
型號(hào): MPC8555EVTAJD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, FLIP CHIP, PLASTIC, BGA-783
文件頁(yè)數(shù): 42/88頁(yè)
文件大?。?/td> 1110K
代理商: MPC8555EVTAJD
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
Freescale Semiconductor
47
CPM
Figure 29 shows TDM input and output signals.
Figure 29. TDM Signal AC Timing Diagram
Figure 30. PIO Signal Diagram
10.3
CPM I2C AC Specification
Table 35. I2C Timing
Characteristic
Expression
All Frequencies
Unit
Min
Max
SCL clock frequency (slave)
fSCL
0FMAX
(1)
Hz
SCL clock frequency (master)
fSCL
BRGCLK/16512
BRGCLK/48
Hz
Bus free time between transmissions
tSDHDL
1/(2.2 * fSCL)-
s
Low period of SCL
tSCLCH
1/(2.2 * fSCL)-
s
High period of SCL
tSCHCL
1/(2.2 * fSCL)-
s
Start condition setup time2
tSCHDL
2/(divider * fSCL)
- (2)
s
Start condition hold time2
tSDLCL
3/(divider * fSCL)-
s
Data hold time
2
tSCLDX
2/(divider * fSCL)-
s
Data setup time2
tSDVCH
3/(divider * fSCL)-
s
SDA/SCL rise time
tSRISE
-1/(10 * fSCL)s
Serial CLKIN
tTDKHOX
TDM Input Signals
There are 4 possible TDM timing conditions:
tTDIVKH
tTDIXKH
TDM Output Signals
Note:
1.
2.
3.
4.
Input sampled on the rising edge and output driven on the rising edge (shown).
Input sampled on the rising edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the falling edge.
Input sampled on the falling edge and output driven on the rising edge.
Sys clk
PIO inputs
PIO outputs
tPIIVKH
tPIIXKH
tPIKHOX
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