參數(shù)資料
型號: MPC8555EPXAJD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA783
封裝: 29 X 29 MM, 3.75 MM HEIGHT, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
文件頁數(shù): 12/88頁
文件大小: 1110K
代理商: MPC8555EPXAJD
MPC8555E PowerQUICC III Integrated Communications Processor Hardware Specification, Rev. 4.2
2
Freescale Semiconductor
Overview
1Overview
The following section provides a high-level overview of the MPC8555E features. Figure 1 shows the
major functional units within the MPC8555E.
Figure 1. MPC8555E Block Diagram
1.1
Key Features
The following lists an overview of the MPC8555E feature set.
Embedded e500 Book E-compatible core
— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture
— Dual-issue superscalar, 7-stage pipeline design
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection
— Lockable L1 caches—entire cache or on a per-line basis
— Separate locking for instructions and data
— Single-precision floating-point operations
— Memory management unit especially designed for embedded applications
— Enhanced hardware and software debug support
— Dynamic power management
— Performance monitor facility
I2C Controller
Local Bus Controller
64/32b PCI Controller
0/32b PCI Controller
DMA Controller
10/100/1000 MAC
MII, GMII, TBI,
RTBI, RGMIIs
Serial
DMA
ROM
I-Memory
DPRAM
RISC
Engine
Parallel I/O
Baud Rate
Generators
Timers
FCC
SCC/USB
SMC
SPI
I2C
T
im
e
-S
lo
tA
ssi
g
n
e
r
S
e
ri
al
I
n
ter
fac
es
MPHY
MIIs/RMIIs
TDMs
I/Os
CPM
DDR SDRAM Controller
CPM
Controller
Interrupt
256-Kbyte
L2 Cache/
SRAM
e500 Core
32-Kbyte L1
I Cache
32-Kbyte L1
D Cache
Core Complex
e500
Coherency
Module
OCeaN
IRQs
SDRAM
DDR
GPIO
32b
Programmable
Interrupt Controller
UTOPIA
Bus
DUART
SCC
SMC
SCC
Security
Engine
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