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參數(shù)資料
| 型號： | MPC8548EHXAUG |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 1333 MHz, MICROPROCESSOR, CBGA783 |
| 封裝： | 29 X 29 MM, 1 MM PITCH, FLIP CHIP, CERAMIC, BGA-783 |
| 文件頁數(shù)： | 36/142頁 |
| 文件大?。?/td> | 1504K |
| 代理商： | MPC8548EHXAUG |
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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
130
Freescale Semiconductor
System Design Information
21.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SVDD and XVDD) to ensure low
jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
First, the board should have at least 10
× 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-F ceramic chip capacitor from each SerDes supply (SVDD and
XVDD) to the board ground plane on each side of the device. This should be done for all SerDes
supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-F, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
21.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. All unused active low inputs should be tied to VDD, TVDD, BVDD, OVDD, GVDD, and LVDD, as
required. All unused active high inputs should be connected to GND. All NC (no-connect) signals must
remain unconnected. Power and ground connections must be made to all external VDD, TVDD, BVDD,
OVDD, GVDD, LVDD, and GND pins of the device.
21.6
Pull-Up and Pull-Down Resistor Requirements
The MPC8548E requires weak pull-up resistors (2–10 k
Ω is recommended) on open drain type pins
including I2C pins and PIC (interrupt) pins.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 62. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
The following pins must not be pulled down during power-on reset: TSEC3_TXD[3], HRESET_REQ,
TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The DMA_DACK[0:1], and TEST_SEL/
TEST_SEL pins must be set to a proper state during POR configuration. Refer to the pinlist table of the
individual device for more details
Refer to the PCI 2.2 specification for all pull ups required for PCI.
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| MPC8547VTAUJB | 32-BIT, 1333 MHz, MICROPROCESSOR, PBGA783 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8548EHXAUJ | 功能描述:微處理器 - MPU PQ38 8548E RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8548EHXAVH | 制造商:Freescale Semiconductor 功能描述:MPU RISC 32BIT CMOS 1.5GHZ 1.8V/2.5V/3.3V - Bulk |
| MPC8548EHXAVK | 制造商:Freescale Semiconductor 功能描述:PQ38 8548E - Bulk |
| MPC8548EPXANJB | 制造商:Freescale Semiconductor 功能描述:PQ38 8548 - Bulk |
| MPC8548EPXAQGA | 制造商:Freescale Semiconductor 功能描述:MPC85XX RISC 32-BIT CMOS 1GHZ 1.8V/2.5V/3.3V 783-PIN BGA TRA - Bulk |
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