參數(shù)資料
型號(hào)： MPC8548ECVTATGB
廠商： Freescale Semiconductor
文件頁數(shù)： 45/151頁
文件大小： 0K
描述： MPU POWERQUICC III 783-PBGA
產(chǎn)品培訓(xùn)模塊： MPC8548 PowerQUICC III Processors
標(biāo)準(zhǔn)包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.2GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 783-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 783-FCPBGA（29x29）
包裝： 托盤
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
139
System Design Information
Figure 61. Driver Impedance Measurement
This table summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,
nominal OVDD, 105C.
22.8
Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 k
on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 k
. This value must permit the 4.7-kresistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor minimizes the disruption of signal quality or speed for output pins thus
configured.
Table 86. Impedance Characteristics
Impedance
Local Bus, Ethernet, DUART, Control,
Configuration, Power Management
PCI
DDR DRAM
Symbol
Unit
RN
43 Target
25 Target
20 Target
Z0
W
RP
43 Target
25 Target
20 Target
Z0
W
Note: Nominal supply voltages. See Table 1, Tj = 105C.
OVDD
OGND
Pad
Data
SW1
SW2
RN
RP
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