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    參數(shù)資料
    型號: MPC8547EPXATJA
    廠商: FREESCALE SEMICONDUCTOR INC
    元件分類: 微控制器/微處理器
    英文描述: 32-BIT, 1200 MHz, MICROPROCESSOR, PBGA783
    封裝: 29 X 29 MM, 1 MM PITCH, FLIP CHIP, PLASTIC, BGA-783
    文件頁數(shù): 105/142頁
    文件大?。?/td> 1504K
    代理商: MPC8547EPXATJA
    MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5
    Freescale Semiconductor
    65
    High-Speed Serial Interfaces (HSSI)
    LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
    clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
    addition to AC-coupling.
    NOTE
    Figure 43 through Figure 46 below are for conceptual reference only. Due
    to the fact that clock driver chip's internal structure, output impedance and
    termination requirements are different between various clock driver chip
    manufacturers, it’s very possible that the clock circuit reference designs
    provided by clock driver chip vendor are different from what is shown
    below. They might also vary from one vendor to the other. Therefore,
    Freescale Semiconductor can neither provide the optimal clock driver
    reference circuits, nor guarantee the correctness of the following clock
    driver connection reference circuits. The system designer is recommended
    to contact the selected clock driver chip vendor for the optimal reference
    circuits with the MPC8548E SerDes reference clock receiver requirement
    provided in this document.
    Figure 43 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
    assumes that the DC levels of the clock driver chip is compatible with MPC8548E SerDes reference clock
    input’s DC requirement.
    Figure 43. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
    Figure 44 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
    Since LVDS clock driver’s common mode voltage is higher than the MPC8548E SerDes reference clock
    input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
    LVDS output driver features 50-
    Ω termination resistor. It also assumes that the LVDS transmitter
    establishes its own common mode level without relying on the receiver or other external component.
    50
    Ω
    50
    Ω
    SD_REF_CLK
    Clock Driver
    100
    Ω Differential PWB Trace
    Clock driver vendor dependent
    source termination resistor
    CLK_Out
    HCSL CLK Driver Chip
    33
    Ω
    33
    Ω
    Total 50
    Ω. Assume clock driver’s
    output impedance is about 16
    Ω.
    MPC8548E
    CLK_Out
    SerDes Refer.
    CLK Receiver
    Clock Driver
    相關(guān)PDF資料
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